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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
09/14/1999
Application #:
09238359
Filing Dt:
01/27/1999
Title:
PRE-AMORPHIZATION PROCESS FOR SOURCE/DRAIN JUNCTION
2
Patent #:
Issue Dt:
07/24/2001
Application #:
09238492
Filing Dt:
01/27/1999
Title:
DUAL CHIP WITH HEAT SINK
3
Patent #:
Issue Dt:
11/19/2002
Application #:
09239322
Filing Dt:
01/28/1999
Title:
SECURITY PROFILE FOR WEB BROWSER
4
Patent #:
Issue Dt:
02/18/2003
Application #:
09239327
Filing Dt:
01/28/1999
Title:
METHOD OF INTEGRATING SUBSTRATE CONTACT ON SOI WAFERS WITH STI PROCESS
5
Patent #:
Issue Dt:
10/03/2000
Application #:
09239487
Filing Dt:
01/28/1999
Title:
DELAY-LOCKED-LOOP (DLL) HAVING SYMMETRICAL RISING AND FALLING CLOCK EDGE TYPE DELAYS
6
Patent #:
Issue Dt:
03/19/2002
Application #:
09240231
Filing Dt:
01/29/1999
Title:
SYSTEM AND METHOD FOR GENERATING TAXONOMIES WITH APPLICATIONS TO CONTENT- BASED RECOMMENDATIONS
7
Patent #:
Issue Dt:
02/25/2003
Application #:
09244416
Filing Dt:
02/04/1999
Title:
MECHANISM FOR ACCUMULATING DATA TO DETERMINE AVERAGE VALUES OF PERFORMANCE PARAMETERS
8
Patent #:
Issue Dt:
03/09/2004
Application #:
09244958
Filing Dt:
02/04/1999
Title:
DISCONTINUOUS DIELECTRIC INTERFACE FOR BIPOLAR TRANSISTORS
9
Patent #:
Issue Dt:
10/30/2001
Application #:
09245161
Filing Dt:
02/04/1999
Title:
STI PUNCH-THROUGH DEFECTS AND STRESS REDUCTION BY HIGH TEMPERATURE OXIDE REFLOW PROCESS
10
Patent #:
Issue Dt:
10/24/2000
Application #:
09245727
Filing Dt:
02/08/1999
Title:
MOSFET WITH GATE PLUG USING DIFFERENTIAL OXIDE GROWTH
11
Patent #:
Issue Dt:
07/10/2001
Application #:
09246462
Filing Dt:
02/09/1999
Title:
ULTRA-THIN GATE OXIDE FORMATION USING AN N2O PLASMA
12
Patent #:
Issue Dt:
07/16/2002
Application #:
09247275
Filing Dt:
02/10/1999
Publication #:
Pub Dt:
02/14/2002
Title:
MOSCAP DESIGN FOR IMPROVED RELIABILITY
13
Patent #:
Issue Dt:
01/15/2002
Application #:
09247334
Filing Dt:
02/10/1999
Title:
AUTOMATIC RECOVERY FROM CLOCK SIGNAL LOSS
14
Patent #:
Issue Dt:
12/09/2003
Application #:
09247659
Filing Dt:
02/10/1999
Title:
MANAGEMENT OF MOVE REQUESTS FROM A FACTORY SYSTEM TO AN AUTOMATED MATERIAL HANDLING SYSTEM
15
Patent #:
Issue Dt:
04/15/2003
Application #:
09247876
Filing Dt:
02/10/1999
Title:
SCALABLE VIRTUAL TIMER ARCHITECTURE FOR EFFICIENTLY IMPLEMENTING MULTIPLE HARDWARE TIMERS WITH MINIMAL SILICON OVERHEAD
16
Patent #:
Issue Dt:
07/10/2001
Application #:
09248432
Filing Dt:
02/11/1999
Title:
METHOD FOR FORMING AN INTEGRATED CIRCUIT MEMORY CELL AND PRODUCT THEREOF
17
Patent #:
Issue Dt:
01/30/2001
Application #:
09248433
Filing Dt:
02/11/1999
Title:
INTEGRATED CIRCUIT TRANSISTOR WITH LOW-RESISTIVITY SOURCE/DRAIN STRUCTURES AT LEAST PARTIALLY RECESSED WITHIN A DIELECTRIC BASE LAYER
18
Patent #:
Issue Dt:
02/20/2001
Application #:
09249988
Filing Dt:
02/13/1999
Title:
DECOUPLING CAPACITOR CONFIGURATION FOR INTEGRATED CIRCUIT CHIP
19
Patent #:
Issue Dt:
05/08/2001
Application #:
09250174
Filing Dt:
02/16/1999
Title:
SEMICONDUCTOR DEVICE WITH A MODULATED GATE OXIDE THICKNESS
20
Patent #:
Issue Dt:
01/23/2001
Application #:
09250308
Filing Dt:
02/16/1999
Title:
ACCUMULATOR FOR SLURRY SAMPLING
21
Patent #:
Issue Dt:
12/04/2001
Application #:
09250880
Filing Dt:
02/16/1999
Title:
APPARATUS AND METHOD FOR NON-CONTACT STRESS EVALUATION OF WAFER GATE DIELECTRIC RELIABILITY
22
Patent #:
Issue Dt:
08/01/2000
Application #:
09250881
Filing Dt:
02/16/1999
Title:
MOSFET STRUCTURE AND PROCESS FOR LOW GATE INDUCED DRAIN LEAKAGE (GIDL)
23
Patent #:
Issue Dt:
09/04/2001
Application #:
09251012
Filing Dt:
02/16/1999
Title:
LOCATION DEPENDENT AUTOMATIC DEFECT CLASSIFICATION
24
Patent #:
Issue Dt:
01/30/2001
Application #:
09251661
Filing Dt:
02/17/1999
Title:
TRIPLE POLYSILICON EMBEDDED NVRAM CELL AND METHOD THEREOF
25
Patent #:
Issue Dt:
04/17/2001
Application #:
09252184
Filing Dt:
02/18/1999
Title:
METHOD OF FORMING LOW DIELECTRIC TUNGSTEN LINED INTERCONNECTION SYSTEM
26
Patent #:
Issue Dt:
02/06/2001
Application #:
09253466
Filing Dt:
02/19/1999
Title:
METHOD AND APPARATUS FOR INSTRUCTION QUEUE COMPRESSION
27
Patent #:
Issue Dt:
07/04/2000
Application #:
09253479
Filing Dt:
02/19/1999
Title:
FABRICATION OF A VIA PLUG HAVING HIGH ASPECT RATIO WITH DIFFUSION BARRIER LAYER EFFECTIVELY SURROUNDING THE VIA PLUG
28
Patent #:
Issue Dt:
06/12/2001
Application #:
09253480
Filing Dt:
02/19/1999
Title:
METHOD FOR FILLING A DUAL DAMASCENE OPENING HAVING HIGH ASPECT RATIO TO MINIMIZE ELECTROMIGRATION FAILURE
29
Patent #:
Issue Dt:
05/01/2001
Application #:
09255203
Filing Dt:
02/22/1999
Title:
STEP DRAIN AND SOURCE JUNCTION FORMATION
30
Patent #:
Issue Dt:
02/06/2001
Application #:
09255604
Filing Dt:
02/22/1999
Title:
PROCESS FOR FORMING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS
31
Patent #:
Issue Dt:
03/27/2001
Application #:
09255917
Filing Dt:
02/23/1999
Title:
HIGH K INTEGRATION OF GATE DIELECTRIC WITH INTEGRATED SPACER FORMATION FOR HIGH SPEED CMOS
32
Patent #:
Issue Dt:
02/27/2001
Application #:
09255998
Filing Dt:
02/23/1999
Title:
APPARATUS AND METHOD TO ENHANCE HOLE FILL IN SUB-MICRON PLATING
33
Patent #:
Issue Dt:
04/22/2008
Application #:
09256034
Filing Dt:
02/23/1999
Title:
MULTILAYERED RESIST SYSTEMS USING TUNED POLYMER FILMS AS UNDERLAYERS AND METHODS OF FABRICATION THEREOF
34
Patent #:
Issue Dt:
06/19/2001
Application #:
09256541
Filing Dt:
02/24/1999
Title:
METHOD OF FABRICATING SUB-MICRON METAL LINES
35
Patent #:
Issue Dt:
04/27/2004
Application #:
09256779
Filing Dt:
02/24/1999
Title:
ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY AND SELECTIVELY DOWN SHIFTING LINK SPEED BASED ON LOCAL CONFIGURATION SIGNALS
36
Patent #:
Issue Dt:
02/10/2004
Application #:
09256780
Filing Dt:
02/24/1999
Title:
ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY BY MONITORING SYMBOL ERRORS ACROSS MULTIPLE DETECTION INTERVALS
37
Patent #:
Issue Dt:
08/14/2001
Application #:
09256781
Filing Dt:
02/24/1999
Title:
METHOD OF FORMING JUNCTION-LEAKAGE FREE METAL SILICIDE IN A SEMICONDUCTOR WAFER BY AMORPHIZATION OF REFACTORY METAL LAYER
38
Patent #:
Issue Dt:
07/03/2001
Application #:
09256782
Filing Dt:
02/24/1999
Title:
METHOD OF FORMING JUNCTION-LEAKAGE FREE METAL SILICIDE IN A SEMICONDUCTOR WAFER BY AMORPHIZATION OF SOURCE AND DRAIN REGIONS
39
Patent #:
Issue Dt:
05/22/2012
Application #:
09256786
Filing Dt:
02/24/1999
Title:
ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY AND AUTOMATICALLY DOWN SHIFTING LINK SPEED
40
Patent #:
Issue Dt:
11/05/2002
Application #:
09257146
Filing Dt:
02/24/1999
Publication #:
Pub Dt:
02/28/2002
Title:
HIERARCHICAL ROW ACTIVATION METHOD FOR BANKING CONTROL IN MULTI-BANK DRAM
41
Patent #:
Issue Dt:
02/05/2008
Application #:
09257521
Filing Dt:
02/25/1999
Title:
COMMUNICATION PROTOCOL PROCESSOR HAVING MULTIPLE MICROPROCESSOR CORES CONNECTED IN SERIES AND DYNAMICALLY REPROGRAMMED DURING OPERATION VIA INSTRUCTIONS TRANSMITTED ALONG THE SAME DATA PATHS USED TO CONVEY COMMUNICATION DATA
42
Patent #:
Issue Dt:
12/04/2001
Application #:
09258763
Filing Dt:
02/26/1999
Title:
VARIABLE SYMBOLIC LINKS FOR A FILE IN A UNIX OPERATING SYSTEM
43
Patent #:
Issue Dt:
04/17/2001
Application #:
09258834
Filing Dt:
02/26/1999
Title:
SEMICONDUCTOR FABRICATION EXTENDED PARTICLE COLLECTION CUP
44
Patent #:
Issue Dt:
12/12/2000
Application #:
09258959
Filing Dt:
03/01/1999
Title:
EXTREME ULTRAVIOLET LITHOGRAPHY REFLECTIVE MASK
45
Patent #:
Issue Dt:
10/03/2000
Application #:
09259977
Filing Dt:
03/01/1999
Title:
METHOD OF MAKING A PRINTED CIRCUIT BOARD HAVING FILLED HOLES AND A FILL MEMBER FOR USE THEREWITH INCLUDING REINFORCEMENT MEANS
46
Patent #:
Issue Dt:
09/04/2001
Application #:
09260255
Filing Dt:
03/02/1999
Title:
METHOD OF FORMING A SUPER-SHALLOW AMORPHOUS LAYER IN SILICON
47
Patent #:
Issue Dt:
03/20/2001
Application #:
09260821
Filing Dt:
03/02/1999
Title:
METHOD FOR FABRICATING A MOSFET DEVICE STRUCTURE WHICH FACILITATES MITIGATION OF JUNCTION CAPACITANCE AND FLOATING BODY EFFECTS
48
Patent #:
Issue Dt:
09/28/2004
Application #:
09260869
Filing Dt:
03/02/1999
Publication #:
Pub Dt:
07/04/2002
Title:
REFLECTIVE LIGHTVALVE
49
Patent #:
Issue Dt:
02/20/2001
Application #:
09261273
Filing Dt:
03/03/1999
Title:
MULTIPLE SEMICONDUCTOR-ON-INSULATOR THRESHOLD VOLTAGE CIRCUIT
50
Patent #:
Issue Dt:
01/30/2001
Application #:
09261515
Filing Dt:
03/03/1999
Title:
THIN FILM TRANSISTORS WITH ORGANIC-INORGANIC HYBRID MATERIALS AS SEMICONDUCTING CHANNELS
51
Patent #:
Issue Dt:
07/10/2001
Application #:
09262214
Filing Dt:
03/04/1999
Title:
DUMMY PATTERNING FOR SEMICONDUCTOR MANUFACTURING PROCESSES
52
Patent #:
Issue Dt:
07/27/2004
Application #:
09262690
Filing Dt:
03/04/1999
Title:
OPEN-BOTTOMED VIA LINER STRUCTURE AND METHOD FOR FABRICATING SAME
53
Patent #:
Issue Dt:
11/06/2001
Application #:
09263557
Filing Dt:
03/08/1999
Title:
MOS TRANSISTOR WITH ASSISTED-GATE FOR ULTRA-LARGE-SCALE INTEGRATION
54
Patent #:
Issue Dt:
03/27/2001
Application #:
09265161
Filing Dt:
03/09/1999
Title:
LOW TEMPERATURE THIN FILM TRANSISTOR FABRICATION
55
Patent #:
Issue Dt:
09/26/2000
Application #:
09266341
Filing Dt:
03/11/1999
Title:
PHOTORESIST COMPOSITIONS WITH CYCLIC OLEFIN POLYMERS AND HYDROPHOBIC NON-STEROIDAL MULTI-ALICYCLIC ADDITIVES
56
Patent #:
Issue Dt:
10/03/2000
Application #:
09266586
Filing Dt:
03/11/1999
Title:
CAPPED SOLDER BUMPS WHICH FORM AN INTERCONNECTION WITH A TAILORED REFLOW MELTING POINT
57
Patent #:
Issue Dt:
10/30/2001
Application #:
09270240
Filing Dt:
03/15/1999
Title:
SYSTEM FOR USING AN INDEPENDENT CLOCK TO COORDINATE ACCESS TO DATA REGISTERS WITHIN A MODULE BETWEEN PERIPHERAL DEVICE AND A HOST SYSTEM
58
Patent #:
Issue Dt:
01/22/2002
Application #:
09272517
Filing Dt:
03/19/1999
Title:
STRESS RELIEVED BALL GRID ARRAY PACKAGE
59
Patent #:
Issue Dt:
04/08/2008
Application #:
09275568
Filing Dt:
03/24/1999
Title:
SIMILARITY SEARCHING OF MOLECULES BASED UPON DESCRIPTOR VECTORS CHARACTERIZING MOLECULAR REGIONS
60
Patent #:
Issue Dt:
05/14/2002
Application #:
09276422
Filing Dt:
03/25/1999
Title:
METHODS FOR IDENTIFYING SOURCES OF PATTERNS IN PROCESSING EFFECTS IN MANUFACTURING
61
Patent #:
Issue Dt:
01/22/2002
Application #:
09276839
Filing Dt:
03/26/1999
Title:
METHOD FOR RAMPED CURRENT DENSITY PLATING OF SEMICONDUCTOR VIAS AND TRENCHES
62
Patent #:
Issue Dt:
07/09/2002
Application #:
09277511
Filing Dt:
03/26/1999
Title:
METHOD FOR FABRICATING HIGH PERMITIVITY DIELECTRIC STACKS HAVING LOW BUFFER OXIDE
63
Patent #:
Issue Dt:
08/06/2002
Application #:
09277699
Filing Dt:
03/26/1999
Publication #:
Pub Dt:
04/25/2002
Title:
WIRING STRUCTURES CONTAINING INTERCONNECTED METAL AND WIRING LEVELS INCLUDING A CONTINOUS, SINGLE CRYSTALLINE OR POLYCRYSTALLINE CONDUCTIVE MATERIAL HAVING ONE OR MORE TWIN BOUNDARIES
64
Patent #:
Issue Dt:
10/01/2002
Application #:
09281079
Filing Dt:
03/30/1999
Title:
DETECTING FULL CONDITIONS IN A QUEUE
65
Patent #:
Issue Dt:
12/12/2000
Application #:
09281905
Filing Dt:
03/31/1999
Title:
DRIVER WITH SWITCHABLE GAIN
66
Patent #:
Issue Dt:
12/03/2002
Application #:
09281975
Filing Dt:
03/31/1999
Title:
FRAME ASSEMBLY IN DEQUEUING BLOCK
67
Patent #:
Issue Dt:
08/15/2000
Application #:
09282033
Filing Dt:
03/30/1999
Title:
METHOD OF MAKING DISPOSABLE CHANNEL MASKING FOR BOTH SOURCE/DRAIN AND LDD IMPLANT AND SUBSEQUENT GATE FABRICATION
68
Patent #:
Issue Dt:
12/30/2008
Application #:
09282141
Filing Dt:
03/31/1999
Title:
PORTABLE COMPUTER SYSTEM WITH THERMAL ENHANCEMENTS AND MULTIPLE POWER MODES OF OPERATION
69
Patent #:
Issue Dt:
09/12/2000
Application #:
09282576
Filing Dt:
03/31/1999
Title:
APPLICATIONS OF MICRO-ELECTRO-MECHANICAL WOBBLE MOTORS AS RADIO FREQUENCY TRANSCEIVER COMPONENTS
70
Patent #:
Issue Dt:
07/13/2004
Application #:
09283387
Filing Dt:
03/31/1999
Publication #:
Pub Dt:
01/02/2003
Title:
METHOD AND SYSTEM FOR GRAPHICS RENDERING USING HARDWARE-EVENT-TRIGGERED EXECUTION OF CAPTURED GRAPHICS HARDWARE INSTRUCTIONS
71
Patent #:
Issue Dt:
09/18/2001
Application #:
09283679
Filing Dt:
04/01/1999
Title:
PROCESS FOR DESIGN AND MANUFACTURE OF FINE LINE CIRCUITS ON PLANARIZED THIN FILM DIELECTRICS AND CIRCUITS MANUFACTURED THEREBY
72
Patent #:
Issue Dt:
12/26/2000
Application #:
09283753
Filing Dt:
04/02/1999
Title:
POLYSILICON GATE HAVING A METAL PLUG FOR REDUCED GATE RESISTANCE WITHIN A TRENCH EXTENDING INTO THE POLYSILICON LAYER OF THE GATE
73
Patent #:
Issue Dt:
06/26/2001
Application #:
09283754
Filing Dt:
04/02/1999
Title:
PLASMA TREATMENT TO REDUCE STRESS CORROSION INDUCED VOIDING OF PATTERNED METAL LAYERS
74
Patent #:
Issue Dt:
01/23/2001
Application #:
09283960
Filing Dt:
04/01/1999
Title:
COMPENSATED-CURRENT MIRROR OFF-CHIP DRIVER
75
Patent #:
Issue Dt:
12/25/2001
Application #:
09285388
Filing Dt:
04/02/1999
Title:
METHOD OF REDUCING STRESS CORROSION INDUCED VOIDING OF PATTERNED METAL LAYERS
76
Patent #:
Issue Dt:
01/15/2002
Application #:
09286987
Filing Dt:
04/07/1999
Title:
COLLISION HANDLING SCHEME FOR DISCRETE MULTI-TONE DATA COMMUNICATIONS NETWORK
77
Patent #:
Issue Dt:
07/08/2003
Application #:
09286997
Filing Dt:
04/07/1999
Title:
ADAPTIVE TRANSMISSION SYSTEM IN A NETWORK
78
Patent #:
Issue Dt:
02/05/2002
Application #:
09287173
Filing Dt:
04/06/1999
Title:
MANAGING VT FOR REDUCED POWER USING A STATUS TABLE
79
Patent #:
Issue Dt:
12/11/2001
Application #:
09288051
Filing Dt:
04/07/1999
Title:
LOW CTE POWER AND GROUND PLANES
80
Patent #:
Issue Dt:
03/04/2003
Application #:
09289950
Filing Dt:
04/13/1999
Title:
NETWORK TRANSCEIVER HAVING MEDIA INDEPENDENT INTERFACE OPERABLE IN A GENERAL PURPOSE SERIAL INTERFACE MODE
81
Patent #:
Issue Dt:
08/06/2002
Application #:
09289951
Filing Dt:
04/13/1999
Title:
NETWORK TRANSCEIVER HAVING CIRCUITRY FOR REFERENCING TRANSMIT DATA TO A SELECTED INPUT CLOCK
82
Patent #:
Issue Dt:
03/23/2004
Application #:
09290048
Filing Dt:
04/12/1999
Title:
ACOUSTIC NOISE SUPPRESSING CIRCUIT BY SELECTIVE ENABLEMENT OF AN INTERPOLATOR
83
Patent #:
Issue Dt:
09/11/2001
Application #:
09290086
Filing Dt:
04/12/1999
Title:
PROCESS FOR FABRICATING A METAL SEMICONDUCTOR DEVICE COMPONENT BY LATERAL OXIDIZATION
84
Patent #:
Issue Dt:
04/03/2001
Application #:
09290087
Filing Dt:
04/12/1999
Title:
PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT USING A SELECTIVE SILICIDATION REACTION
85
Patent #:
Issue Dt:
11/27/2001
Application #:
09290088
Filing Dt:
04/12/1999
Title:
PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT BY OXIDIZING A SILICON HARD MASK
86
Patent #:
Issue Dt:
07/10/2001
Application #:
09290311
Filing Dt:
04/12/1999
Title:
POLYMER ENHANCED COLUMN GRID ARRAY
87
Patent #:
Issue Dt:
04/10/2001
Application #:
09290555
Filing Dt:
04/12/1999
Title:
PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT USING LATERAL METAL OXIDATION
88
Patent #:
Issue Dt:
10/10/2000
Application #:
09290784
Filing Dt:
04/13/1999
Title:
PARTICLE BEAM SYSTEM WITH DYNAMIC FOCUSING
89
Patent #:
Issue Dt:
10/31/2000
Application #:
09291036
Filing Dt:
04/14/1999
Title:
AUTO-NEGOTIATION USING NEGATIVE LINK PULSES
90
Patent #:
Issue Dt:
04/17/2001
Application #:
09291040
Filing Dt:
04/14/1999
Title:
POLISHING PAD AND METHOD FOR POLISHING POROUS MATERIALS
91
Patent #:
Issue Dt:
08/07/2001
Application #:
09291138
Filing Dt:
04/12/1999
Title:
MODIFIED MATERIAL DEPOSITION SEQUENCE FOR REDUCED DETECT DENSITIES IN SEMICONDUCTOR MANUFACTURING
92
Patent #:
Issue Dt:
04/02/2002
Application #:
09291389
Filing Dt:
04/13/1999
Title:
BLENDS OF HYDROXYSTYRENE POLYMERS FOR USE IN CHEMICALLY AMPLIFIED POSITIVE RESIST FORMULATIONS
93
Patent #:
Issue Dt:
08/08/2000
Application #:
09291984
Filing Dt:
04/14/1999
Title:
FAST CHIP ERASE MODE FOR NON-VOLATILE MEMORY
94
Patent #:
Issue Dt:
01/30/2001
Application #:
09292769
Filing Dt:
04/14/1999
Title:
SYSTEM FOR MAKING ELECTROPHORETIC DIES WHILE REDUCING DAMAGE DUE TO ELECTROSTATIC CHARGE
95
Patent #:
Issue Dt:
07/16/2002
Application #:
09292913
Filing Dt:
04/16/1999
Title:
METHOD OF FORMING ELECTRODE FOR HIGH PERFORMANCE SEMICONDUCTOR DEVICES
96
Patent #:
Issue Dt:
08/15/2000
Application #:
09293559
Filing Dt:
04/15/1999
Title:
METHOD OF IMPROVING CU DAMASCENE INTERCONNECT RELIABILITY BY LASER ANNEAL BEFORE BARRIER POLISH
97
Patent #:
Issue Dt:
02/05/2002
Application #:
09294076
Filing Dt:
04/19/1999
Title:
SELF-ALIGNED DAMASCENE INTERCONNECT
98
Patent #:
Issue Dt:
11/09/2004
Application #:
09294178
Filing Dt:
04/19/1999
Publication #:
Pub Dt:
04/24/2003
Title:
METHOD FOR STATICALLY TIMING SOI DEVICES AND CIRCUITS
99
Patent #:
Issue Dt:
05/22/2001
Application #:
09295271
Filing Dt:
04/20/1999
Title:
RESIST REMOVAL BY POLISHING
100
Patent #:
Issue Dt:
05/29/2001
Application #:
09295357
Filing Dt:
04/21/1999
Title:
WIRE BONDING CU INTERCONNECTS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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