|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11112527
|
Filing Dt:
|
04/22/2005
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
METHOD TO DIFFERENTIALLY CONTROL LC VOLTAGE-CONTROLLED OSCILLATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11112820
|
Filing Dt:
|
04/22/2005
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11115606
|
Filing Dt:
|
04/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
METHOD AND APPARATUS TO DISABLE COMPACTION OF TEST RESPONSES IN DETERMINISTIC TEST-SET EMBEDDING-BASED BIST
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11116053
|
Filing Dt:
|
04/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH MIXED-CRYSTAL-ORIENTATION CHANNEL AND SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11116625
|
Filing Dt:
|
04/28/2005
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR REDUCING MEMORY ERRORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11116700
|
Filing Dt:
|
04/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
MEMORY AND LOGIC DEVICES USING ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11117276
|
Filing Dt:
|
04/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11121454
|
Filing Dt:
|
05/04/2005
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
11122152
|
Filing Dt:
|
05/04/2005
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
Title:
|
Method and apparatus for dynamic manipulation and dispersion in photonic crystal devices
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11124247
|
Filing Dt:
|
05/06/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11124324
|
Filing Dt:
|
05/06/2005
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
Title:
|
METHOD OF CREATING DEEP TRENCH CAPACITOR USING A P+ METAL ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11124978
|
Filing Dt:
|
05/09/2005
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
Title:
|
SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11125063
|
Filing Dt:
|
05/09/2005
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
Title:
|
DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11125456
|
Filing Dt:
|
05/10/2005
|
Title:
|
SYSTEM AND METHOD FOR TRACE MESSAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11125696
|
Filing Dt:
|
05/10/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11125971
|
Filing Dt:
|
05/09/2005
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
PHOTORESISTS FOR VISIBLE LIGHT IMAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11126675
|
Filing Dt:
|
05/11/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11127175
|
Filing Dt:
|
05/12/2005
|
Title:
|
POLYMER SPACERS FOR CREATING SUB-LITHOGRAPHIC SPACES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11128069
|
Filing Dt:
|
05/12/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11128389
|
Filing Dt:
|
05/13/2005
|
Title:
|
SYSTEM AND METHOD FOR IMPROVING OXIDE-NITRIDE-OXIDE (ONO) COUPLING IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11129784
|
Filing Dt:
|
05/16/2005
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
GENIE: A METHOD FOR CLASSIFICATION AND GRAPHICAL DISPLAY OF NEGATIVE SLACK TIMING TEST FAILURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11129785
|
Filing Dt:
|
05/16/2005
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
NEGATIVE SLACK RECOVERABILITY FACTOR - A NET WEIGHT TO ENHANCE TIMING CLOSURE BEHAVIOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11130078
|
Filing Dt:
|
05/16/2005
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
PROCESS FOR PREPARING ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTILAYER HARDMASK SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11130459
|
Filing Dt:
|
05/16/2005
|
Title:
|
METHOD AND APPARATUS FOR FAST DISTURBANCE DETECTION AND CLASSIFICIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11131534
|
Filing Dt:
|
05/18/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
CIRCUITS AND METHODS FOR IMPLEMENTING POWER AMPLIFIERS FOR MILLIMETER WAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
11135227
|
Filing Dt:
|
05/23/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11135720
|
Filing Dt:
|
05/24/2005
|
Publication #:
|
|
Pub Dt:
|
04/13/2006
| | | | |
Title:
|
CHIP BOND LAYOUT FOR CHIP CARRIER FOR FLIP CHIP APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11136256
|
Filing Dt:
|
05/24/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11136872
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHOD FOR AN EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11137234
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11137245
|
Filing Dt:
|
05/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11137957
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
SUPPORTED GREENSHEET STRUCTURE AND METHOD IN MLC PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11138797
|
Filing Dt:
|
05/26/2005
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
DEVICE COMPRISING DOPED NANO-COMPONENT AND METHOD OF FORMING THE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11140780
|
Filing Dt:
|
05/31/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
11140803
|
Filing Dt:
|
05/31/2005
|
Title:
|
SERIAL INTERFACE HAVING A READ TEMPERATURE COMMAND
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11142566
|
Filing Dt:
|
06/01/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR REDUCED LEAKAGE AND IMPROVED PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11146441
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR FAR END NOISE REDUCTION USING CAPACITIVE CANCELLATION BY OFFSET WIRING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11146495
|
Filing Dt:
|
06/06/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
PLANAR ARRAY CONTACT MEMORY CARDS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11146863
|
Filing Dt:
|
06/07/2005
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
MICROPROCESSOR INCLUDING A CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11147003
|
Filing Dt:
|
06/07/2005
|
Title:
|
HYSTERISIS MANAGEMENT FOR DELAY LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
11147383
|
Filing Dt:
|
06/08/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
RAISED SOURCE AND DRAIN PROCESS WITH DISPOSABLE SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11148737
|
Filing Dt:
|
06/09/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11150188
|
Filing Dt:
|
06/13/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
METHOD AND STRUCTURE FOR HIGH PERFORMANCE PHASE CHANGE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11150565
|
Filing Dt:
|
06/10/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
ANTIREFLECTIVE FILM-FORMING COMPOSITION, METHOD FOR MANUFACTURING THE SAME, AND ANTIREFLECTIVE FILM AND PATTERN FORMATION METHOD USING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
11151007
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
Title:
|
MEMORY DEVICE AND METHOD OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11151317
|
Filing Dt:
|
06/14/2005
|
Title:
|
PCI-X ERROR CORRECTING CODE (ECC) PIN SHARING CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11151318
|
Filing Dt:
|
06/14/2005
|
Title:
|
CONTROL OF PCI MEMORY READ BEHAVIOR USING MEMORY READ ALIAS AND MEMORY COMMAND REISSUE BITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11151470
|
Filing Dt:
|
06/13/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTIONS WITH IMPROVED TUNNELING MAGNETO-RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11151480
|
Filing Dt:
|
06/13/2005
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
Title:
|
LITHOGRAPHY TOOL IMAGE QUALITY EVALUATING AND CORRECTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11151550
|
Filing Dt:
|
06/14/2005
|
Title:
|
STRAINED-SILICON DEVICE WITH DIFFERENT SILICON THICKNESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11151830
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11151843
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS WITH FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11151905
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
COOLING STRUCTURE USING RIGID MOVABLE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11152750
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
REPROGRAMMABLE FUSE STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11153047
|
Filing Dt:
|
06/15/2005
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
CAPACITANCE MODELING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
11153570
|
Filing Dt:
|
06/13/2005
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11154905
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
Title:
|
METHOD AND APPARATUS TO SIMULATE AND VERIFY SIGNAL GLITCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11155030
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11157090
|
Filing Dt:
|
06/20/2005
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
METHOD AND APPARATUS OF CAPACITY LEARNING FOR COMPUTER SYSTEMS AND APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11158726
|
Filing Dt:
|
06/22/2005
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
Title:
|
HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11159946
|
Filing Dt:
|
06/23/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
TOPCOAT COMPOSITIONS AND METHODS OF USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
11160054
|
Filing Dt:
|
06/07/2005
|
Title:
|
SENSE AMPLIFIER INCLUDING MULTIPLE CONDUCTION STATE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11160151
|
Filing Dt:
|
06/10/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
SECURE ELECTRICALLY PROGRAMMABLE FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11160156
|
Filing Dt:
|
06/10/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
IMMERSION LITHOGRAPHY WITH EQUALIZED PRESSURE ON AT LEAST PROJECTION OPTICS COMPONENT AND WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11160184
|
Filing Dt:
|
08/19/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
SELECTIVELY CHANGEABLE LINE WIDTH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11160268
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
ENABLING MEMORY REDUNDANCY DURING TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
11160273
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11160307
|
Filing Dt:
|
06/17/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
NESTED DESIGN APPROACH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11160361
|
Filing Dt:
|
06/21/2005
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
SUBSTRATE BACKGATE FOR TRIGATE FET
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
11160428
|
Filing Dt:
|
06/23/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
CURRENT-ALIGNED AUTO-GENERATED NON-EQUIAXIAL HOLE SHAPE FOR WIRING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
11160457
|
Filing Dt:
|
06/24/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
DENSE PITCH BULK FINFET PROCESS BY SELECTIVE EPI AND ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
11160463
|
Filing Dt:
|
06/24/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11160468
|
Filing Dt:
|
06/24/2005
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
METHOD AND STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11160667
|
Filing Dt:
|
07/05/2005
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
APPARATUS AND METHOD FOR SELECTED SITE BACKSIDE UNDERLAYING OF Si, GaAs, Gax Aly Asz OF SOI TECHNOLOGIES FOR SCANNING PROBE MICROSCOPY AND ATOMIC FORCE PROBING CHARACTERIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11160676
|
Filing Dt:
|
07/05/2005
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
SELF-ALIGNED DUAL STRESSED LAYERS FOR NFET AND PFET
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11160700
|
Filing Dt:
|
07/06/2005
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
METHOD FOR FORMING SEMICONDUCTOR DEVICES HAVING REDUCED GATE EDGE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
11160956
|
Filing Dt:
|
07/18/2005
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
VERTICAL PNP TRANSISTOR AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11160997
|
Filing Dt:
|
07/19/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
THERMAL PASTE CONTAINMENT FOR SEMICONDUCTOR MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11161066
|
Filing Dt:
|
07/21/2005
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN PFETS WITH EMBEDDED SIGE SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11161146
|
Filing Dt:
|
07/25/2005
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11161183
|
Filing Dt:
|
07/26/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
NON-VOLATILE SWITCHING AND MEMORY DEVICES USING VERTICAL NANOTUBES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11161213
|
Filing Dt:
|
07/27/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
VIRTUAL BODY-CONTACTED TRIGATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11161214
|
Filing Dt:
|
07/27/2005
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHOD FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11161239
|
Filing Dt:
|
07/27/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHOD OF FORMING A VERTICAL P-N JUNCTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
11161321
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
Title:
|
APPARATUS AND METHOD FOR DYNAMIC CONTROL OF DOUBLE GATE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11161330
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
SUPERVISORY OPERATING SYSTEM FOR RUNNING MULTIPLE CHILD OPERATING SYSTEMS SIMULTANEOUSLY AND OPTIMIZING RESOURCE USAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11161337
|
Filing Dt:
|
07/29/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR IMPROVING INTEGRATED CIRCUIT DEVICE PERFORMANCE USING HYBRID CRYSTAL ORIENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11161414
|
Filing Dt:
|
08/02/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
INTER-CHIP ESD PROTECTION STRUCTURE FOR HIGH SPEED AND HIGH FREQUENCY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11161415
|
Filing Dt:
|
08/02/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
METHOD FOR HIGH PERFORMANCE INDUCTOR FABRICATION USING A TRIPLE DAMASCENE PROCESS WITH COPPER BEOL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11161599
|
Filing Dt:
|
08/09/2005
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
Title:
|
VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
11161628
|
Filing Dt:
|
08/10/2005
|
Title:
|
DRAM WITH SELF-RESETTING DATA PATH FOR REDUCED POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11161630
|
Filing Dt:
|
08/10/2005
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
Title:
|
EVAPORATION CONTROL USING COATING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11161742
|
Filing Dt:
|
08/15/2005
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
Title:
|
VOLTAGE CONTROLLED STATIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11161832
|
Filing Dt:
|
08/18/2005
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
Title:
|
INTEGRATED BEOL THIN FILM RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
11161932
|
Filing Dt:
|
08/23/2005
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
11161936
|
Filing Dt:
|
08/23/2005
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR HAVING INTERSTITIAL TRAPPING LAYER IN BASE REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11161962
|
Filing Dt:
|
08/24/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11162126
|
Filing Dt:
|
08/30/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11162196
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD OF FACILITATING INTEGRATED CIRCUIT DESIGN USING MANUFACTURED PROPERTY VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11162413
|
Filing Dt:
|
09/09/2005
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME
|
|