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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 34 of 146
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1
Patent #:
7361950
Issue Dt:
04/22/2008
Application #:
11162471
Filing Dt:
09/12/2005
Publication #:
US20070057343
Pub Dt:
03/15/2007
Title:
INTEGRATION OF A MIM CAPACITOR WITH A PLATE FORMED IN A WELL REGION AND WITH A HIGH-K DIELECTRIC
2
Patent #:
7227233
Issue Dt:
06/05/2007
Application #:
11162472
Filing Dt:
09/12/2005
Publication #:
US20070057323
Pub Dt:
03/15/2007
Title:
SILICON-ON-INSULATOR (SOI) READ ONLY MEMORY (ROM) ARRAY AND METHOD OF MAKING A SOI ROM
3
Patent #:
7394154
Issue Dt:
07/01/2008
Application #:
11162513
Filing Dt:
09/13/2005
Publication #:
US20070057374
Pub Dt:
03/15/2007
Title:
EMBEDDED BARRIER FOR DIELECTRIC ENCAPSULATION
4
Patent #:
7400031
Issue Dt:
07/15/2008
Application #:
11162660
Filing Dt:
09/19/2005
Publication #:
US20070063230
Pub Dt:
03/22/2007
Title:
ASYMMETRICALLY STRESSED CMOS FINFET
5
Patent #:
8207568
Issue Dt:
06/26/2012
Application #:
11162661
Filing Dt:
09/19/2005
Publication #:
US20070065966
Pub Dt:
03/22/2007
Title:
PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
6
Patent #:
7323374
Issue Dt:
01/29/2008
Application #:
11162663
Filing Dt:
09/19/2005
Publication #:
US20070063276
Pub Dt:
03/22/2007
Title:
DENSE CHEVRON FINFET AND METHOD OF MANUFACTURING SAME
7
Patent #:
7563704
Issue Dt:
07/21/2009
Application #:
11162666
Filing Dt:
09/19/2005
Publication #:
US20070063348
Pub Dt:
03/22/2007
Title:
METHOD OF FORMING AN INTERCONNECT INCLUDING A DIELECTRIC CAP HAVING A TENSILE STRESS
8
Patent #:
8202460
Issue Dt:
06/19/2012
Application #:
11162765
Filing Dt:
09/22/2005
Publication #:
US20070063392
Pub Dt:
03/22/2007
Title:
MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT
9
Patent #:
7279426
Issue Dt:
10/09/2007
Application #:
11162766
Filing Dt:
09/22/2005
Publication #:
US20070066073
Pub Dt:
03/22/2007
Title:
LIKE INTEGRATED CIRCUIT DEVICES WITH DIFFERENT DEPTH
10
Patent #:
7388244
Issue Dt:
06/17/2008
Application #:
11162776
Filing Dt:
09/22/2005
Publication #:
US20070063244
Pub Dt:
03/22/2007
Title:
TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME
11
Patent #:
7605447
Issue Dt:
10/20/2009
Application #:
11162780
Filing Dt:
09/22/2005
Publication #:
US20070063278
Pub Dt:
03/22/2007
Title:
HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION
12
Patent #:
7308663
Issue Dt:
12/11/2007
Application #:
11162846
Filing Dt:
09/26/2005
Publication #:
US20070074135
Pub Dt:
03/29/2007
Title:
CIRCUIT DESIGN VERIFICATION USING CHECKPOINTING
13
Patent #:
7894291
Issue Dt:
02/22/2011
Application #:
11162847
Filing Dt:
09/26/2005
Publication #:
US20070070769
Pub Dt:
03/29/2007
Title:
CIRCUIT AND METHOD FOR CONTROLLING A STANDBY VOLTAGE LEVEL OF A MEMORY
14
Patent #:
7202513
Issue Dt:
04/10/2007
Application #:
11162953
Filing Dt:
09/29/2005
Publication #:
US20070069294
Pub Dt:
03/29/2007
Title:
STRESS ENGINEERING USING DUAL PAD NITRIDE WITH SELECTIVE SOI DEVICE ARCHITECTURE
15
Patent #:
7282949
Issue Dt:
10/16/2007
Application #:
11162997
Filing Dt:
09/30/2005
Publication #:
US20070075733
Pub Dt:
04/05/2007
Title:
FPGA POWERUP TO KNOWN FUNCTIONAL STATE
16
Patent #:
7396713
Issue Dt:
07/08/2008
Application #:
11163165
Filing Dt:
10/07/2005
Publication #:
US20070080401
Pub Dt:
04/12/2007
Title:
STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
17
Patent #:
7344679
Issue Dt:
03/18/2008
Application #:
11163327
Filing Dt:
10/14/2005
Publication #:
US20070086927
Pub Dt:
04/19/2007
Title:
METHOD AND APPARATUS FOR POINT OF CARE OSMOLARITY TESTING
18
Patent #:
7221024
Issue Dt:
05/22/2007
Application #:
11163686
Filing Dt:
10/27/2005
Publication #:
US20070096223
Pub Dt:
05/03/2007
Title:
TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS FOR APPLYING IN-PLANE SHEAR STRESS
19
Patent #:
7348225
Issue Dt:
03/25/2008
Application #:
11163687
Filing Dt:
10/27/2005
Publication #:
US20070099350
Pub Dt:
05/03/2007
Title:
STRUCTURE AND METHOD OF FABRICATING FINFET WITH BURIED CHANNEL
20
Patent #:
7386815
Issue Dt:
06/10/2008
Application #:
11163696
Filing Dt:
10/27/2005
Publication #:
US20070099236
Pub Dt:
05/03/2007
Title:
TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
21
Patent #:
7286425
Issue Dt:
10/23/2007
Application #:
11163800
Filing Dt:
10/31/2005
Publication #:
US20070097768
Pub Dt:
05/03/2007
Title:
SYSTEM AND METHOD FOR CAPACITIVE MIS-MATCH BIT-LINE SENSING
22
Patent #:
7287740
Issue Dt:
10/30/2007
Application #:
11163835
Filing Dt:
11/01/2005
Publication #:
US20070114505
Pub Dt:
05/24/2007
Title:
HOISTING APPARATUS
23
Patent #:
7655511
Issue Dt:
02/02/2010
Application #:
11163908
Filing Dt:
11/03/2005
Publication #:
US20070096206
Pub Dt:
05/03/2007
Title:
GATE ELECTRODE STRESS CONTROL FOR FINFET PERFORMANCE ENHANCEMENT
24
Patent #:
7397260
Issue Dt:
07/08/2008
Application #:
11163948
Filing Dt:
11/04/2005
Publication #:
US20070115018
Pub Dt:
05/24/2007
Title:
STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS
25
Patent #:
7335563
Issue Dt:
02/26/2008
Application #:
11164070
Filing Dt:
11/09/2005
Publication #:
US20070105326
Pub Dt:
05/10/2007
Title:
ROTATED FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURE
26
Patent #:
7633106
Issue Dt:
12/15/2009
Application #:
11164072
Filing Dt:
11/09/2005
Publication #:
US20070102738
Pub Dt:
05/10/2007
Title:
LIGHT SHIELD FOR CMOS IMAGER
27
Patent #:
7492015
Issue Dt:
02/17/2009
Application #:
11164109
Filing Dt:
11/10/2005
Publication #:
US20070102747
Pub Dt:
05/10/2007
Title:
COMPLEMENTARY CARBON NANOTUBE TRIPLE GATE TECHNOLOGY
28
Patent #:
7250666
Issue Dt:
07/31/2007
Application #:
11164214
Filing Dt:
11/15/2005
Publication #:
US20070108534
Pub Dt:
05/17/2007
Title:
SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
29
Patent #:
7326976
Issue Dt:
02/05/2008
Application #:
11164216
Filing Dt:
11/15/2005
Publication #:
US20070108537
Pub Dt:
05/17/2007
Title:
CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR
30
Patent #:
7378717
Issue Dt:
05/27/2008
Application #:
11164217
Filing Dt:
11/15/2005
Publication #:
US20070108473
Pub Dt:
05/17/2007
Title:
SEMICONDUCTOR OPTICAL SENSORS
31
Patent #:
7183613
Issue Dt:
02/27/2007
Application #:
11164224
Filing Dt:
11/15/2005
Title:
METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM
32
Patent #:
7408206
Issue Dt:
08/05/2008
Application #:
11164377
Filing Dt:
11/21/2005
Publication #:
US20070115606
Pub Dt:
05/24/2007
Title:
METHOD AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS
33
Patent #:
7655972
Issue Dt:
02/02/2010
Application #:
11164378
Filing Dt:
11/21/2005
Publication #:
US20070114611
Pub Dt:
05/24/2007
Title:
STRUCTURE AND METHOD FOR MOSFET WITH REDUCED EXTENSION RESISTANCE
34
Patent #:
7427545
Issue Dt:
09/23/2008
Application #:
11164381
Filing Dt:
11/21/2005
Publication #:
US20070117307
Pub Dt:
05/24/2007
Title:
TRENCH MEMORY CELLS WITH BURIED ISOLATION COLLARS, AND METHODS OF FABRICATING SAME
35
Patent #:
7977185
Issue Dt:
07/12/2011
Application #:
11164417
Filing Dt:
11/22/2005
Publication #:
US20070161244
Pub Dt:
07/12/2007
Title:
METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL
36
Patent #:
7514323
Issue Dt:
04/07/2009
Application #:
11164513
Filing Dt:
11/28/2005
Publication #:
US20070122971
Pub Dt:
05/31/2007
Title:
VERTICAL SOI TRENCH SONOS CELL
37
Patent #:
7816738
Issue Dt:
10/19/2010
Application #:
11164651
Filing Dt:
11/30/2005
Publication #:
US20070122957
Pub Dt:
05/31/2007
Title:
LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES
38
Patent #:
7871933
Issue Dt:
01/18/2011
Application #:
11164684
Filing Dt:
12/01/2005
Publication #:
US20070128859
Pub Dt:
06/07/2007
Title:
COMBINED STEPPER AND DEPOSITION TOOL
39
Patent #:
7608909
Issue Dt:
10/27/2009
Application #:
11164765
Filing Dt:
12/05/2005
Publication #:
US20060197119
Pub Dt:
09/07/2006
Title:
SUSPENDED TRANSMISSION LINE STRUCTURES IN BACK END OF LINE PROCESSING
40
Patent #:
7368712
Issue Dt:
05/06/2008
Application #:
11164792
Filing Dt:
12/06/2005
Publication #:
US20070125946
Pub Dt:
06/07/2007
Title:
Y-SHAPED CARBON NANOTUBES AS AFM PROBE FOR ANALYZING SUBSTRATES WITH ANGLED TOPOGRAPHY
41
Patent #:
7202128
Issue Dt:
04/10/2007
Application #:
11165330
Filing Dt:
06/24/2005
Title:
METHOD OF FORMING A MEMORY DEVICE HAVING IMPROVED ERASE SPEED
42
Patent #:
7199309
Issue Dt:
04/03/2007
Application #:
11167662
Filing Dt:
06/27/2005
Publication #:
US20050239347
Pub Dt:
10/27/2005
Title:
STRUCTURE FOR REPAIRING OR MODIFYING SURFACE CONNECTIONS ON CIRCUIT BOARDS
43
Patent #:
7411425
Issue Dt:
08/12/2008
Application #:
11168691
Filing Dt:
06/28/2005
Publication #:
US20060290382
Pub Dt:
12/28/2006
Title:
METHOD FOR POWER CONSUMPTION REDUCTION IN A LIMITED-SWITCH DYNAMIC LOGIC (LSDL) CIRCUIT
44
Patent #:
7336105
Issue Dt:
02/26/2008
Application #:
11168692
Filing Dt:
06/28/2005
Publication #:
US20060290383
Pub Dt:
12/28/2006
Title:
DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC
45
Patent #:
7319608
Issue Dt:
01/15/2008
Application #:
11172473
Filing Dt:
06/30/2005
Publication #:
US20070002608
Pub Dt:
01/04/2007
Title:
NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS
46
Patent #:
7419907
Issue Dt:
09/02/2008
Application #:
11173038
Filing Dt:
07/01/2005
Publication #:
US20070004205
Pub Dt:
01/04/2007
Title:
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE
47
Patent #:
7262422
Issue Dt:
08/28/2007
Application #:
11173257
Filing Dt:
07/01/2005
Publication #:
US20070026345
Pub Dt:
02/01/2007
Title:
USE OF SUPERCRITICAL FLUID TO DRY WAFER AND CLEAN LENS IN IMMERSION LITHOGRAPHY
48
Patent #:
8144478
Issue Dt:
03/27/2012
Application #:
11173388
Filing Dt:
07/01/2005
Title:
CIRCUIT MODULE AND METHOD
49
Patent #:
7060549
Issue Dt:
06/13/2006
Application #:
11174400
Filing Dt:
07/01/2005
Title:
SRAM DEVICES UTILIZING TENSILE-STRESSED STRAIN FILMS AND METHODS FOR FABRICATING THE SAME
50
Patent #:
7348226
Issue Dt:
03/25/2008
Application #:
11174738
Filing Dt:
07/06/2005
Publication #:
US20050266663
Pub Dt:
12/01/2005
Title:
METHOD OF FORMING LATTICE-MATCHED STRUCTURE ON SILICON AND STRUCTURE FORMED THEREBY
51
Patent #:
7994575
Issue Dt:
08/09/2011
Application #:
11175582
Filing Dt:
07/06/2005
Publication #:
US20050242378
Pub Dt:
11/03/2005
Title:
METAL-OXIDE-SEMICONDUCTOR DEVICE STRUCTURES WITH TAILORED DOPANT DEPTH PROFILES
52
Patent #:
7346875
Issue Dt:
03/18/2008
Application #:
11176712
Filing Dt:
07/07/2005
Publication #:
US20050262463
Pub Dt:
11/24/2005
Title:
WIRING OPTIMIZATIONS FOR POWER
53
Patent #:
7331007
Issue Dt:
02/12/2008
Application #:
11177127
Filing Dt:
07/07/2005
Publication #:
US20070011631
Pub Dt:
01/11/2007
Title:
HARNESSING MACHINE LEARNING TO IMPROVE THE SUCCESS RATE OF STIMULI GENERATION
54
Patent #:
7265420
Issue Dt:
09/04/2007
Application #:
11179282
Filing Dt:
07/12/2005
Publication #:
US20050263753
Pub Dt:
12/01/2005
Title:
SEMICONDUCTOR SUBSTRATE LAYER CONFIGURED FOR INDUCEMENT OF COMPRESSIVE OR EXPANSIVE FORCE
55
Patent #:
7266737
Issue Dt:
09/04/2007
Application #:
11180416
Filing Dt:
07/13/2005
Publication #:
US20070033459
Pub Dt:
02/08/2007
Title:
METHOD FOR ENABLING SCAN OF DEFECTIVE RAM PRIOR TO REPAIR
56
Patent #:
7376924
Issue Dt:
05/20/2008
Application #:
11180740
Filing Dt:
07/13/2005
Publication #:
US20060010413
Pub Dt:
01/12/2006
Title:
METHODS FOR PLACEMENT WHICH MAINTAIN OPTIMIZED BEHAVIOR, WHILE IMPROVING WIREABILITY POTENTIAL
57
Patent #:
7326442
Issue Dt:
02/05/2008
Application #:
11180788
Filing Dt:
07/14/2005
Publication #:
US20070015083
Pub Dt:
01/18/2007
Title:
ANTIREFLECTIVE COMPOSITION AND PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE
58
Patent #:
7417453
Issue Dt:
08/26/2008
Application #:
11181053
Filing Dt:
07/14/2005
Publication #:
US20050251778
Pub Dt:
11/10/2005
Title:
SYSTEM AND METHOD FOR DYNAMICALLY EXECUTING A FUNCTION IN A PROGRAMMABLE LOGIC ARRAY
59
Patent #:
7756219
Issue Dt:
07/13/2010
Application #:
11181152
Filing Dt:
07/14/2005
Publication #:
US20060067429
Pub Dt:
03/30/2006
Title:
LOW-IF MULTIPLE MODE TRANSMITTER FRONT END AND CORRESPONDING METHOD
60
Patent #:
7425855
Issue Dt:
09/16/2008
Application #:
11181707
Filing Dt:
07/14/2005
Publication #:
US20070013426
Pub Dt:
01/18/2007
Title:
SET/RESET LATCH WITH MINIMUM SINGLE EVENT UPSET
61
Patent #:
7382162
Issue Dt:
06/03/2008
Application #:
11181954
Filing Dt:
07/14/2005
Publication #:
US20070013413
Pub Dt:
01/18/2007
Title:
HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS
62
Patent #:
7378350
Issue Dt:
05/27/2008
Application #:
11182445
Filing Dt:
07/15/2005
Publication #:
US20050266681
Pub Dt:
12/01/2005
Title:
FORMATION OF LOW RESISTANCE VIA CONTACTS IN INTERCONNECT STRUCTURES
63
Patent #:
7289422
Issue Dt:
10/30/2007
Application #:
11182558
Filing Dt:
07/15/2005
Publication #:
US20050254355
Pub Dt:
11/17/2005
Title:
OPTICAL DEVICES HAVING TRANSMISSION ENHANCED BY SURFACE PLASMON MODE RESONANCE, AND THEIR USE IN DATA RECORDING
64
Patent #:
7405131
Issue Dt:
07/29/2008
Application #:
11182681
Filing Dt:
07/16/2005
Publication #:
US20070020864
Pub Dt:
01/25/2007
Title:
METHOD AND STRUCTURE TO PREVENT SILICIDE STRAPPING OF SOURCE/DRAIN TO BODY IN SEMICONDUCTOR DEVICES WITH SOURCE/DRAIN STRESSOR
65
Patent #:
7442618
Issue Dt:
10/28/2008
Application #:
11182682
Filing Dt:
07/16/2005
Publication #:
US20070020861
Pub Dt:
01/25/2007
Title:
METHOD TO ENGINEER ETCH PROFILES IN SI SUBSTRATE FOR ADVANCED SEMICONDUCTOR DEVICES
66
Patent #:
7381635
Issue Dt:
06/03/2008
Application #:
11183647
Filing Dt:
07/18/2005
Publication #:
US20070013073
Pub Dt:
01/18/2007
Title:
METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS
67
Patent #:
7468320
Issue Dt:
12/23/2008
Application #:
11183773
Filing Dt:
07/19/2005
Publication #:
US20050266673
Pub Dt:
12/01/2005
Title:
REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF COPPER WIRES BY SURFACE COATING
68
Patent #:
7342287
Issue Dt:
03/11/2008
Application #:
11184244
Filing Dt:
07/19/2005
Publication #:
US20070018248
Pub Dt:
01/25/2007
Title:
POWER GATING SCHEMES IN SOI CIRCUITS IN HYBRID SOI-EPITAXIAL CMOS STRUCTURES
69
Patent #:
7354777
Issue Dt:
04/08/2008
Application #:
11184702
Filing Dt:
07/19/2005
Publication #:
US20050255707
Pub Dt:
11/17/2005
Title:
DISCRETE NANO-TEXTURED STRUCTURES IN BIOMOLECULAR ARRAYS, AND METHOD OF USE
70
Patent #:
8759894
Issue Dt:
06/24/2014
Application #:
11189765
Filing Dt:
07/27/2005
Title:
System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device
71
Patent #:
7674521
Issue Dt:
03/09/2010
Application #:
11190360
Filing Dt:
07/27/2005
Publication #:
US20070196639
Pub Dt:
08/23/2007
Title:
MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE
72
Patent #:
7464255
Issue Dt:
12/09/2008
Application #:
11192153
Filing Dt:
07/28/2005
Title:
USING A SHUFFLE UNIT TO IMPLEMENT SHIFT OPERATIONS IN A PROCESSOR
73
Patent #:
7636780
Issue Dt:
12/22/2009
Application #:
11192259
Filing Dt:
07/28/2005
Publication #:
US20070027988
Pub Dt:
02/01/2007
Title:
VERIFIED COMPUTING ENVIRONMENT FOR PERSONAL INTERNET COMMUNICATOR
74
Patent #:
7315765
Issue Dt:
01/01/2008
Application #:
11192691
Filing Dt:
07/29/2005
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Title:
PROGRAMMABLE RANDOM LOGIC ARRAYS USING PN ISOLATION
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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