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02/26/2008
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Application #:
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11254044
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Filing Dt:
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10/19/2005
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Publication #:
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Pub Dt:
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04/19/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR MAKING COPLANAR ISOLATED REGIONS OF DIFFERENT SEMICONDUCTOR MATERIALS ON A SUBSTRATE
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Patent #:
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Issue Dt:
|
10/13/2009
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Application #:
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11255971
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Filing Dt:
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10/24/2005
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Title:
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METHOD FOR FORMING SOLDER JOINTS FOR A FLIP CHIP ASSEMBLY
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11257904
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Filing Dt:
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10/25/2005
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Publication #:
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Pub Dt:
|
09/06/2007
| | | | |
Title:
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APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES
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Patent #:
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Issue Dt:
|
08/05/2008
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Application #:
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11259315
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Filing Dt:
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10/26/2005
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Publication #:
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Pub Dt:
|
04/26/2007
| | | | |
Title:
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IMPORTATION OF VIRTUAL SIGNALS INTO ELECTRONIC TEST EQUIPMENT TO FACILITATE TESTING OF AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
|
12/30/2008
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Application #:
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11259483
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Filing Dt:
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10/26/2005
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Publication #:
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Pub Dt:
|
03/02/2006
| | | | |
Title:
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STRUCTURE AND METHOD TO FABRICATE FINFET DEVICES
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Patent #:
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Issue Dt:
|
08/18/2009
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Application #:
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11259572
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Filing Dt:
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10/26/2005
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Title:
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SYSTEM FOR CHARACTERIZATION OF LOW-K DIELECTRIC MATERIAL DAMAGE
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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11259644
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Filing Dt:
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10/26/2005
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Publication #:
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Pub Dt:
|
04/26/2007
| | | | |
Title:
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LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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11259654
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Filing Dt:
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10/26/2005
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Publication #:
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Pub Dt:
|
04/26/2007
| | | | |
Title:
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METHOD FOR TUNING EPITAXIAL GROWTH BY INTERFACIAL DOPING AND STRUCTURE INCLUDING SAME
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Patent #:
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Issue Dt:
|
05/06/2008
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Application #:
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11262101
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Filing Dt:
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10/28/2005
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Publication #:
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Pub Dt:
|
05/03/2007
| | | | |
Title:
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IMPEDANCE CALIBRATION FOR SOURCE SERIES TERMINATED SERIAL LINK TRANSMITTER
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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11262134
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Filing Dt:
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10/28/2005
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
Title:
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NON-ORIENTED WIRE IN ELASTOMER ELECTRICAL CONTACT
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Patent #:
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Issue Dt:
|
12/11/2007
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Application #:
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11263138
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Filing Dt:
|
10/27/2005
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Publication #:
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Pub Dt:
|
05/10/2007
| | | | |
Title:
|
SELF SERIES TERMINATED SERIAL LINK TRANSMITTER HAVING SEGMENTATION FOR AMPLITUDE, PRE-EMPHASIS, AND SLEW RATE CONTROL AND VOLTAGE REGULATION FOR AMPLITUDE ACCURACY AND HIGH VOLTAGE PROTECTION
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Patent #:
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Issue Dt:
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09/29/2009
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Application #:
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11263189
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Filing Dt:
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10/31/2005
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Publication #:
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Pub Dt:
|
05/03/2007
| | | | |
Title:
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APPARATUS, SYSTEM, AND METHOD FOR ADAPTIVE ASYNCHRONOUS EQUALIZATION USING LEAKAGE
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Patent #:
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Issue Dt:
|
10/02/2007
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Application #:
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11263430
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Filing Dt:
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10/31/2005
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
Title:
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SILICON-CONTAINING COMPOSITIONS FOR SPIN-ON ARC/HARDMASK MATERIALS
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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11264446
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Filing Dt:
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11/01/2005
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
Title:
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MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
|
05/05/2009
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Application #:
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11266456
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Filing Dt:
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11/03/2005
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Publication #:
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Pub Dt:
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05/03/2007
| | | | |
Title:
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ACCESSIBLE CHIP STACK AND PROCESS OF MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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11266741
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Filing Dt:
|
11/03/2005
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Publication #:
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Pub Dt:
|
05/03/2007
| | | | |
Title:
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METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS
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Patent #:
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Issue Dt:
|
12/30/2008
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Application #:
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11267882
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Filing Dt:
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11/04/2005
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
Title:
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METHOD OF MAKING A FINFET HAVING SUPPRESSED PARASITIC DEVICE CHARACTERISTICS
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Patent #:
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Issue Dt:
|
10/16/2007
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Application #:
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11268106
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Filing Dt:
|
11/07/2005
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
Title:
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LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME
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Patent #:
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Issue Dt:
|
12/30/2008
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Application #:
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11268132
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Filing Dt:
|
11/07/2005
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Publication #:
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Pub Dt:
|
05/10/2007
| | | | |
Title:
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METHODS OF FORMING FIELD EFFECT TRANSISTORS USING DISPOSABLE ALUMINUM OXIDE SPACERS
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Patent #:
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Issue Dt:
|
07/14/2009
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Application #:
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11270029
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Filing Dt:
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11/08/2005
|
Title:
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PROTECTION ELEMENT AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
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11270708
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Filing Dt:
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11/09/2005
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Publication #:
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Pub Dt:
|
04/13/2006
| | | | |
Title:
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METHOD OF FORMING AN INTEGRATED CIRCUIT STRUCTURE ON A HYBRID CRYSTAL ORIENTED SUBSTRATE
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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11271032
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Filing Dt:
|
11/10/2005
|
Publication #:
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|
Pub Dt:
|
05/18/2006
| | | | |
Title:
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PROCESS OPTIONS OF FORMING SILICIDED METAL GATES FOR ADVANCED CMOS DEVICES
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Patent #:
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Issue Dt:
|
04/01/2008
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Application #:
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11272884
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Filing Dt:
|
11/14/2005
|
Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
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DATA PROCESSING IN DIGITAL SYSTEMS
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|
Patent #:
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Issue Dt:
|
06/10/2008
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Application #:
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11275010
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Filing Dt:
|
12/01/2005
|
Publication #:
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Pub Dt:
|
06/14/2007
| | | | |
Title:
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MEMORY DEVICES USING CARBON NANOTUBE (CNT) TECHNOLOGIES
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Patent #:
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Issue Dt:
|
10/28/2008
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Application #:
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11275035
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Filing Dt:
|
12/05/2005
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Publication #:
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Pub Dt:
|
06/07/2007
| | | | |
Title:
|
AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS
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Patent #:
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Issue Dt:
|
06/14/2016
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Application #:
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11275091
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Filing Dt:
|
12/09/2005
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Publication #:
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Pub Dt:
|
06/14/2007
| | | | |
Title:
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METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT
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Patent #:
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Issue Dt:
|
12/07/2010
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Application #:
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11275092
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Filing Dt:
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12/09/2005
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Publication #:
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Pub Dt:
|
07/19/2007
| | | | |
Title:
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METHOD AND SYSTEM OF COHERENT DESIGN VERIFICATION OF INTER-CLUSTER INTERACTIONS
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Patent #:
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Issue Dt:
|
10/26/2010
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Application #:
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11275417
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Filing Dt:
|
12/30/2005
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Publication #:
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Pub Dt:
|
07/05/2007
| | | | |
Title:
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PIXEL ARRAY, IMAGING SENSOR INCLUDING THE PIXEL ARRAY AND DIGITAL CAMERA INCLUDING THE IMAGING SENSOR
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Patent #:
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Issue Dt:
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12/30/2008
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Application #:
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11275482
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Filing Dt:
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01/09/2006
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Publication #:
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Pub Dt:
|
04/27/2006
| | | | |
Title:
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INTEGRATED CIRCUIT STRUCTURES FOR PREVENTING CHARGING DAMAGE
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Patent #:
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Issue Dt:
|
04/14/2009
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Application #:
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11275492
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Filing Dt:
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01/10/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
Title:
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SRAM ARRAY AND ANALOG FET WITH DUAL-STRAIN LAYERS COMPRISING RELAXED REGIONS
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Patent #:
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Issue Dt:
|
01/06/2009
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Application #:
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11275514
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Filing Dt:
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01/11/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
Title:
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SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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11275540
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Filing Dt:
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01/13/2006
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Publication #:
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Pub Dt:
|
05/11/2006
| | | | |
Title:
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MEMORY ARRAY REPAIR WHERE REPAIR LOGIC CANNOT OPERATE AT SAME OPERATING CONDITION AS ARRAY
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Patent #:
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Issue Dt:
|
10/13/2009
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Application #:
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11275604
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Filing Dt:
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01/19/2006
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Publication #:
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Pub Dt:
|
08/16/2007
| | | | |
Title:
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DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
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Patent #:
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Issue Dt:
|
11/20/2007
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Application #:
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11275638
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Filing Dt:
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01/20/2006
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Publication #:
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Pub Dt:
|
07/26/2007
| | | | |
Title:
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ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
|
10/28/2008
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Application #:
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11275644
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Filing Dt:
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01/20/2006
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Publication #:
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Pub Dt:
|
07/26/2007
| | | | |
Title:
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STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS
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Patent #:
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Issue Dt:
|
02/01/2011
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Application #:
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11276236
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Filing Dt:
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02/20/2006
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Publication #:
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Pub Dt:
|
08/23/2007
| | | | |
Title:
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PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS
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Patent #:
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Issue Dt:
|
03/22/2011
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Application #:
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11276282
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Filing Dt:
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02/22/2006
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Publication #:
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Pub Dt:
|
08/23/2007
| | | | |
Title:
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METHOD OF FABRICATING A PRECISION BURIED RESISTOR
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11276366
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Filing Dt:
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02/27/2006
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Publication #:
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Pub Dt:
|
08/30/2007
| | | | |
Title:
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MULTI-ORIENTATION SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE, AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
|
07/14/2009
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Application #:
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11276369
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Filing Dt:
|
02/27/2006
|
Publication #:
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Pub Dt:
|
08/30/2007
| | | | |
Title:
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HIGH PERFORMANCE TAPERED VARACTOR
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Patent #:
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Issue Dt:
|
08/14/2007
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Application #:
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11276380
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Filing Dt:
|
02/27/2006
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Publication #:
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|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
CHIP UNDERFILL IN FLIP-CHIP TECHNOLOGIES
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|