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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 49 of 146
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1
Patent #:
7609569
Issue Dt:
10/27/2009
Application #:
11941994
Filing Dt:
11/19/2007
Publication #:
US20090129181
Pub Dt:
05/21/2009
Title:
SYSTEM AND METHOD FOR IMPLEMENTING ROW REDUNDANCY WITH REDUCED ACCESS TIME AND REDUCED DEVICE AREA
2
Patent #:
7900181
Issue Dt:
03/01/2011
Application #:
11942148
Filing Dt:
11/19/2007
Publication #:
US20080072196
Pub Dt:
03/20/2008
Title:
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
3
Patent #:
7844435
Issue Dt:
11/30/2010
Application #:
11942270
Filing Dt:
11/19/2007
Publication #:
US20080072189
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT CHIP HAVING ON-CHIP SIGNAL INTEGRITY AND NOISE VERIFICATION USING FREQUENCY DEPENDENT RLC EXTRACTION AND MODELING TECHNIQUES
4
Patent #:
7860701
Issue Dt:
12/28/2010
Application #:
11942309
Filing Dt:
11/19/2007
Publication #:
US20080071512
Pub Dt:
03/20/2008
Title:
METHODOLOGY FOR IMAGE FIDELITY VERIFICATION
5
Patent #:
7727827
Issue Dt:
06/01/2010
Application #:
11942400
Filing Dt:
11/19/2007
Publication #:
US20080242040
Pub Dt:
10/02/2008
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
6
Patent #:
7865855
Issue Dt:
01/04/2011
Application #:
11942744
Filing Dt:
11/20/2007
Publication #:
US20090064069
Pub Dt:
03/05/2009
Title:
METHOD AND SYSTEM FOR GENERATING A LAYOUT FOR AN INTEGRATED ELECTRONIC CIRCUIT
7
Patent #:
7862987
Issue Dt:
01/04/2011
Application #:
11942753
Filing Dt:
11/20/2007
Publication #:
US20090130599
Pub Dt:
05/21/2009
Title:
METHOD FOR FORMING AN ELECTRICAL STRUCTURE COMPRISING MULTIPLE PHOTOSENSITIVE MATERIALS
8
Patent #:
8017995
Issue Dt:
09/13/2011
Application #:
11942756
Filing Dt:
11/20/2007
Publication #:
US20090127619
Pub Dt:
05/21/2009
Title:
DEEP TRENCH SEMICONDUCTOR STRUCTURE AND METHOD
9
Patent #:
7923808
Issue Dt:
04/12/2011
Application #:
11942811
Filing Dt:
11/20/2007
Publication #:
US20090127652
Pub Dt:
05/21/2009
Title:
STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING
10
Patent #:
7895556
Issue Dt:
02/22/2011
Application #:
11942990
Filing Dt:
11/20/2007
Publication #:
US20090132982
Pub Dt:
05/21/2009
Title:
METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES
11
Patent #:
7882465
Issue Dt:
02/01/2011
Application #:
11944408
Filing Dt:
11/21/2007
Publication #:
US20080116919
Pub Dt:
05/22/2008
Title:
FPGA AND METHOD AND SYSTEM FOR CONFIGURING AND DEBUGGING A FPGA
12
Patent #:
7955892
Issue Dt:
06/07/2011
Application #:
11944625
Filing Dt:
11/25/2007
Publication #:
US20090134511
Pub Dt:
05/28/2009
Title:
MULTIPLE SIZE PACKAGE SOCKET
13
Patent #:
7861209
Issue Dt:
12/28/2010
Application #:
11944769
Filing Dt:
11/26/2007
Publication #:
US20080086715
Pub Dt:
04/10/2008
Title:
METHOD FOR INTERLAYER AND YIELD BASED OPTICAL PROXIMITY CORRECTION
14
Patent #:
7877559
Issue Dt:
01/25/2011
Application #:
11944864
Filing Dt:
11/26/2007
Publication #:
US20090138659
Pub Dt:
05/28/2009
Title:
MECHANISM TO ACCELERATE REMOVAL OF STORE OPERATIONS FROM A QUEUE
15
Patent #:
8006042
Issue Dt:
08/23/2011
Application #:
11944878
Filing Dt:
11/26/2007
Publication #:
US20090138662
Pub Dt:
05/28/2009
Title:
FLOATING POINT BYPASS RETRY
16
Patent #:
7458048
Issue Dt:
11/25/2008
Application #:
11945069
Filing Dt:
11/26/2007
Publication #:
US20080077379
Pub Dt:
03/27/2008
Title:
COMPUTER PROGRAM PRODUCT FOR VERIFICATION OF DIGITAL DESIGNS USING CASE-SPLITTING VIA CONSTRAINED INTERNAL SIGNALS
17
Patent #:
7913202
Issue Dt:
03/22/2011
Application #:
11945308
Filing Dt:
11/27/2007
Publication #:
US20080068039
Pub Dt:
03/20/2008
Title:
WAFER LEVEL I/O TEST, REPAIR AND/OR CUSTOMIZATION ENABLED BY I/O LAYER
18
Patent #:
7912568
Issue Dt:
03/22/2011
Application #:
11945700
Filing Dt:
11/27/2007
Publication #:
US20090138117
Pub Dt:
05/28/2009
Title:
TUNING ORDER CONFIGURATOR PERFORMANCE BY DYNAMIC INTEGRATION OF MANUFACTURING AND FIELD FEEDBACK
19
Patent #:
8037337
Issue Dt:
10/11/2011
Application #:
11946096
Filing Dt:
11/28/2007
Publication #:
US20090138676
Pub Dt:
05/28/2009
Title:
DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS
20
Patent #:
8148953
Issue Dt:
04/03/2012
Application #:
11946550
Filing Dt:
11/28/2007
Publication #:
US20090134844
Pub Dt:
05/28/2009
Title:
APPARATUS AND METHOD FOR RECYCLING AND REUSING CHARGE IN AN ELECTRONIC CIRCUIT
21
Patent #:
8004060
Issue Dt:
08/23/2011
Application #:
11946938
Filing Dt:
11/29/2007
Publication #:
US20090141533
Pub Dt:
06/04/2009
Title:
METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE
22
Patent #:
7602635
Issue Dt:
10/13/2009
Application #:
11947092
Filing Dt:
11/29/2007
Publication #:
US20090141536
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR A CONFIGURABLE SRAM SYSTEM AND METHOD
23
Patent #:
7883395
Issue Dt:
02/08/2011
Application #:
11947103
Filing Dt:
11/29/2007
Publication #:
US20090142994
Pub Dt:
06/04/2009
Title:
ELECTRICAL CONTACT STRUCTURES AND METHODS FOR USE
24
Patent #:
8120175
Issue Dt:
02/21/2012
Application #:
11947832
Filing Dt:
11/30/2007
Publication #:
US20090140420
Pub Dt:
06/04/2009
Title:
SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE
25
Patent #:
7909208
Issue Dt:
03/22/2011
Application #:
11947856
Filing Dt:
11/30/2007
Publication #:
US20090139451
Pub Dt:
06/04/2009
Title:
PROCESS OF MONITORING DISPENSING OF PROCESS FLUIDS IN PRECISION PROCESSING OPERATIONS
26
Patent #:
7863169
Issue Dt:
01/04/2011
Application #:
11947929
Filing Dt:
11/30/2007
Publication #:
US20090140350
Pub Dt:
06/04/2009
Title:
LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES
27
Patent #:
7829460
Issue Dt:
11/09/2010
Application #:
11948245
Filing Dt:
11/30/2007
Publication #:
US20080179741
Pub Dt:
07/31/2008
Title:
METHOD OF MANUFRACTURING INCREASING RELIABILITY OF COPPER-BASED METALLIZATION STRUCTURES IN A MICROSTRUCTURE DEVICE BY USING ALUMINUM NITRIDE
28
Patent #:
7873921
Issue Dt:
01/18/2011
Application #:
11948308
Filing Dt:
11/30/2007
Publication #:
US20090144689
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR A VOLTAGE DETECTION CIRCUIT IN AN INTEGRATED CIRCUIT AND METHOD OF GENERATING A TRIGGER FLAG SIGNAL
29
Patent #:
7948535
Issue Dt:
05/24/2011
Application #:
11948463
Filing Dt:
11/30/2007
Publication #:
US20090141155
Pub Dt:
06/04/2009
Title:
HIGH DYNAMIC RANGE IMAGING CELL WITH ELECTRONIC SHUTTER EXTENSIONS
30
Patent #:
7848128
Issue Dt:
12/07/2010
Application #:
11949063
Filing Dt:
12/03/2007
Publication #:
US20090141527
Pub Dt:
06/04/2009
Title:
APPARATUS AND METHOD FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES
31
Patent #:
7924588
Issue Dt:
04/12/2011
Application #:
11949065
Filing Dt:
12/03/2007
Publication #:
US20090141528
Pub Dt:
06/04/2009
Title:
CONTENT ADDRESSABLE MEMORY WITH CONCURRENT TWO-DIMENSIONAL SEARCH CAPABILITY IN BOTH ROW AND COLUMN DIRECTIONS
32
Patent #:
8196088
Issue Dt:
06/05/2012
Application #:
11949066
Filing Dt:
12/03/2007
Publication #:
US20090144024
Pub Dt:
06/04/2009
Title:
METHOD AND STRUCTURE FOR SCREENING NFET-TO-PFET DEVICE PERFORMANCE OFFSETS WITHIN A CMOS PROCESS
33
Patent #:
7646648
Issue Dt:
01/12/2010
Application #:
11949068
Filing Dt:
12/03/2007
Publication #:
US20090141537
Pub Dt:
06/04/2009
Title:
APPARATUS AND METHOD FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATIONAL CAPABILITY
34
Patent #:
7624289
Issue Dt:
11/24/2009
Application #:
11949129
Filing Dt:
12/03/2007
Publication #:
US20080091961
Pub Dt:
04/17/2008
Title:
POWER NETWORK RECONFIGURATION USING MEM SWITCHES
35
Patent #:
8268542
Issue Dt:
09/18/2012
Application #:
11949190
Filing Dt:
12/03/2007
Publication #:
US20090142704
Pub Dt:
06/04/2009
Title:
METHOD FOR REDUCING SIDE LOBE PRINTING USING A BARRIER LAYER
36
Patent #:
7432755
Issue Dt:
10/07/2008
Application #:
11949426
Filing Dt:
12/03/2007
Title:
PROGRAMMING CURRENT STABILIZED ELECTRICAL FUSE PROGRAMMING CIRCUIT AND METHOD
37
Patent #:
7880266
Issue Dt:
02/01/2011
Application #:
11949569
Filing Dt:
12/03/2007
Publication #:
US20080073749
Pub Dt:
03/27/2008
Title:
A FOUR-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT.
38
Patent #:
8024513
Issue Dt:
09/20/2011
Application #:
11949904
Filing Dt:
12/04/2007
Publication #:
US20090144506
Pub Dt:
06/04/2009
Title:
METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE
39
Patent #:
8174010
Issue Dt:
05/08/2012
Application #:
11949993
Filing Dt:
12/04/2007
Publication #:
US20080265247
Pub Dt:
10/30/2008
Title:
UNIFIED TEST STRUCTURE FOR STRESS MIGRATION TESTS
40
Patent #:
7956412
Issue Dt:
06/07/2011
Application #:
11950001
Filing Dt:
12/04/2007
Publication #:
US20090140343
Pub Dt:
06/04/2009
Title:
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE
41
Patent #:
8784966
Issue Dt:
07/22/2014
Application #:
11950453
Filing Dt:
12/05/2007
Publication #:
US20080113169
Pub Dt:
05/15/2008
Title:
METHOD OF FORMING A MATERIAL HAVING A PREDEFINED MORPHOLOGY
42
Patent #:
7989357
Issue Dt:
08/02/2011
Application #:
11950741
Filing Dt:
12/05/2007
Publication #:
US20090146221
Pub Dt:
06/11/2009
Title:
METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF
43
Patent #:
7979250
Issue Dt:
07/12/2011
Application #:
11950747
Filing Dt:
12/05/2007
Publication #:
US20090150123
Pub Dt:
06/11/2009
Title:
METHOD OF LAYING OUT A DATA CENTER USING A PLURALITY OF THERMAL SIMULATORS
44
Patent #:
7832925
Issue Dt:
11/16/2010
Application #:
11950758
Filing Dt:
12/05/2007
Publication #:
US20090150129
Pub Dt:
06/11/2009
Title:
APPARATUS AND METHOD FOR SIMULATING HEATED AIRFLOW EXHAUST OF AN ELECTRONICS SUBSYSTEM, ELECTRONICS RACK OR ROW OF ELECTRONICS RACKS
45
Patent #:
7912106
Issue Dt:
03/22/2011
Application #:
11950939
Filing Dt:
12/05/2007
Publication #:
US20090147818
Pub Dt:
06/11/2009
Title:
ENHANCED SURFACE-EMITTING PHOTONIC DEVICE
46
Patent #:
7741191
Issue Dt:
06/22/2010
Application #:
11951092
Filing Dt:
12/05/2007
Publication #:
US20080265365
Pub Dt:
10/30/2008
Title:
METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS
47
Patent #:
7904849
Issue Dt:
03/08/2011
Application #:
11951705
Filing Dt:
12/06/2007
Publication #:
US20080092101
Pub Dt:
04/17/2008
Title:
CERAMIC PACKAGE IN WHICH FAR END NOISE IS REDUCED USING CAPACITIVE CANCELLATION BY OFFSET WIRING
48
Patent #:
8613973
Issue Dt:
12/24/2013
Application #:
11951858
Filing Dt:
12/06/2007
Publication #:
US20090145482
Pub Dt:
06/11/2009
Title:
PHOTOVOLTAIC DEVICE WITH SOLUTION-PROCESSED CHALCOGENIDE ABSORBER LAYER
49
Patent #:
7469395
Issue Dt:
12/23/2008
Application #:
11952544
Filing Dt:
12/07/2007
Publication #:
US20080074147
Pub Dt:
03/27/2008
Title:
WIRING OPTIMIZATIONS FOR POWER
50
Patent #:
8062951
Issue Dt:
11/22/2011
Application #:
11953445
Filing Dt:
12/10/2007
Publication #:
US20090146263
Pub Dt:
06/11/2009
Title:
METHOD TO INCREASE EFFECTIVE MOSFET WIDTH
51
Patent #:
7494912
Issue Dt:
02/24/2009
Application #:
11953927
Filing Dt:
12/11/2007
Publication #:
US20080090407
Pub Dt:
04/17/2008
Title:
TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME
52
Patent #:
8137791
Issue Dt:
03/20/2012
Application #:
11954557
Filing Dt:
12/12/2007
Publication #:
US20090155541
Pub Dt:
06/18/2009
Title:
FUSE AND PAD STRESS RELIEF
53
Patent #:
7904839
Issue Dt:
03/08/2011
Application #:
11954646
Filing Dt:
12/12/2007
Publication #:
US20090158444
Pub Dt:
06/18/2009
Title:
SYSTEM AND METHOD FOR CONTROLLING ACCESS TO ADDRESSABLE INTEGRATED CIRCUITS
54
Patent #:
8772933
Issue Dt:
07/08/2014
Application #:
11954812
Filing Dt:
12/12/2007
Publication #:
US20090152723
Pub Dt:
06/18/2009
Title:
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
55
Patent #:
8089160
Issue Dt:
01/03/2012
Application #:
11954866
Filing Dt:
12/12/2007
Publication #:
US20090152724
Pub Dt:
06/18/2009
Title:
IC INTERCONNECT FOR HIGH CURRENT
56
Patent #:
8030709
Issue Dt:
10/04/2011
Application #:
11954918
Filing Dt:
12/12/2007
Publication #:
US20090179283
Pub Dt:
07/16/2009
Title:
METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES
57
Patent #:
7834442
Issue Dt:
11/16/2010
Application #:
11954943
Filing Dt:
12/12/2007
Publication #:
US20090179322
Pub Dt:
07/16/2009
Title:
ELECTRONIC PACKAGE METHOD AND STRUCTURE WITH CURE-MELT HIERARCHY
58
Patent #:
7838198
Issue Dt:
11/23/2010
Application #:
11955451
Filing Dt:
12/13/2007
Publication #:
US20090155718
Pub Dt:
06/18/2009
Title:
PHOTORESIST COMPOSITIONS AND METHOD FOR MULTIPLE EXPOSURES WITH MULTIPLE LAYER RESIST SYSTEMS
59
Patent #:
8053306
Issue Dt:
11/08/2011
Application #:
11955491
Filing Dt:
12/13/2007
Publication #:
US20090152637
Pub Dt:
06/18/2009
Title:
PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT
60
Patent #:
7883976
Issue Dt:
02/08/2011
Application #:
11955515
Filing Dt:
12/13/2007
Publication #:
US20090152646
Pub Dt:
06/18/2009
Title:
STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH PLANAR HALO PROFILE
61
Patent #:
7984394
Issue Dt:
07/19/2011
Application #:
11955580
Filing Dt:
12/13/2007
Publication #:
US20100211923
Pub Dt:
08/19/2010
Title:
DESIGN STRUCTURE FOR A REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
62
Patent #:
7859013
Issue Dt:
12/28/2010
Application #:
11955591
Filing Dt:
12/13/2007
Publication #:
US20080093629
Pub Dt:
04/24/2008
Title:
METAL OXIDE FIELD EFFECT TRANSISTOR WITH A SHARP HALO
63
Patent #:
8021925
Issue Dt:
09/20/2011
Application #:
11955598
Filing Dt:
12/13/2007
Publication #:
US20080299707
Pub Dt:
12/04/2008
Title:
THERMAL PASTE CONTAINMENT FOR SEMICONDUCTOR MODULES
64
Patent #:
8001503
Issue Dt:
08/16/2011
Application #:
11955689
Filing Dt:
12/13/2007
Publication #:
US20090158225
Pub Dt:
06/18/2009
Title:
METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY
65
Patent #:
7893485
Issue Dt:
02/22/2011
Application #:
11955913
Filing Dt:
12/13/2007
Publication #:
US20090158234
Pub Dt:
06/18/2009
Title:
VERTICAL SOI TRENCH SONOS CELL
66
Patent #:
8120095
Issue Dt:
02/21/2012
Application #:
11955940
Filing Dt:
12/13/2007
Publication #:
US20090158226
Pub Dt:
06/18/2009
Title:
HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
67
Patent #:
7861192
Issue Dt:
12/28/2010
Application #:
11955976
Filing Dt:
12/13/2007
Publication #:
US20090158076
Pub Dt:
06/18/2009
Title:
A TECHNIQUE TO IMPLEMENT CLOCK-GATING USING A COMMON ENABLE FOR A PLURALITY OF STORAGE CELLS
68
Patent #:
7863646
Issue Dt:
01/04/2011
Application #:
11956043
Filing Dt:
12/13/2007
Publication #:
US20090152638
Pub Dt:
06/18/2009
Title:
DUAL OXIDE STRESS LINER
69
Patent #:
9054074
Issue Dt:
06/09/2015
Application #:
11957576
Filing Dt:
12/17/2007
Publication #:
US20090154107
Pub Dt:
06/18/2009
Title:
ONE-DIMENSIONAL HIERARCHICAL NESTED CHANNEL DESIGN FOR CONTINUOUS FEED MANUFACTURING PROCESSES
70
Patent #:
7872901
Issue Dt:
01/18/2011
Application #:
11957797
Filing Dt:
12/17/2007
Publication #:
US20080152932
Pub Dt:
06/26/2008
Title:
PROGRAMMABLE-RESISTANCE MEMORY CELL
71
Patent #:
7831813
Issue Dt:
11/09/2010
Application #:
11957848
Filing Dt:
12/17/2007
Publication #:
US20090158015
Pub Dt:
06/18/2009
Title:
USES OF KNOWN GOOD CODE FOR IMPLEMENTING PROCESSOR ARCHITECTURAL MODIFICATIONS
72
Patent #:
8114736
Issue Dt:
02/14/2012
Application #:
11958254
Filing Dt:
12/17/2007
Publication #:
US20080150042
Pub Dt:
06/26/2008
Title:
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
73
Patent #:
7925369
Issue Dt:
04/12/2011
Application #:
11958448
Filing Dt:
12/18/2007
Publication #:
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Title:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Title:
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Title:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Pub Dt:
07/09/2009
Title:
SYSTEM FOR MEASURING AN EYEWIDTH OF A DATA SIGNAL IN AN ASYNCHRONOUS SYSTEM
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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