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07/12/2011
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12108992
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04/24/2008
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04/30/2009
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Title:
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DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
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04/26/2011
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12109025
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04/24/2008
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Pub Dt:
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10/29/2009
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Title:
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SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS
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03/08/2011
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12109379
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04/25/2008
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Pub Dt:
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10/29/2009
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Title:
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DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF
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12/28/2010
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12110375
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04/28/2008
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Pub Dt:
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06/04/2009
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Title:
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DESIGN STRUCTURE FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES
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02/14/2012
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12110456
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04/28/2008
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Pub Dt:
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06/04/2009
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Title:
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STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY
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01/25/2011
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12110465
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04/28/2008
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09/25/2008
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Title:
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METHOD AND STRUCTURE FOR SELF-ALIGNED DEVICE CONTACTS
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08/30/2011
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12110579
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04/28/2008
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Pub Dt:
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10/29/2009
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Title:
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BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CIRCUITS
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Patent #:
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10/19/2010
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12110633
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06/20/2008
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10/09/2008
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING LAMINATED ISOLATION REGION
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09/27/2011
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12110639
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04/28/2008
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Pub Dt:
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10/29/2009
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Title:
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METHODS AND APPARATUS FOR DETERMINING A SWITCHING HISTORY TIME CONSTANT IN AN INTEGRATED CIRCUIT DEVICE
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06/19/2012
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12110644
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04/28/2008
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09/25/2008
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Title:
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RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE
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07/13/2010
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12110698
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04/28/2008
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Pub Dt:
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11/13/2008
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Title:
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APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS OF PHYSICAL CHARACTERISTICS WITHIN A DATA CENTER
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06/15/2010
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12110732
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04/28/2008
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Pub Dt:
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10/02/2008
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Title:
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METHOD AND APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS OF PHYSICAL CHARACTERISTICS WITHIN A DATA CENTER
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09/27/2011
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12110765
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04/28/2008
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Pub Dt:
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09/04/2008
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Title:
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STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE
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11/16/2010
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12110851
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04/28/2008
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Pub Dt:
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10/29/2009
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Title:
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METHOD FOR MONITORING DEPENDENT METRIC STREAMS FOR ANOMALIES
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07/03/2012
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12111276
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04/29/2008
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Pub Dt:
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10/29/2009
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Title:
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SLURRYLESS MECHANICAL PLANARIZATION FOR SUBSTRATE RECLAMATION
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01/25/2011
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12111529
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04/29/2008
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Pub Dt:
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08/21/2008
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Title:
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COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE
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Patent #:
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04/19/2011
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12111609
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04/29/2008
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Pub Dt:
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08/21/2008
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Title:
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STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH ELEMENT
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Patent #:
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06/07/2011
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12112329
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04/30/2008
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Pub Dt:
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11/05/2009
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Title:
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STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT
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Patent #:
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Issue Dt:
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08/23/2011
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12112336
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Filing Dt:
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04/30/2008
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Publication #:
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Pub Dt:
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11/05/2009
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Title:
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IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION
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Patent #:
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Issue Dt:
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05/31/2011
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12112391
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Filing Dt:
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04/30/2008
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Pub Dt:
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11/05/2009
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Title:
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SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS
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Patent #:
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Issue Dt:
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02/09/2010
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12112454
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Filing Dt:
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04/30/2008
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Publication #:
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Pub Dt:
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11/05/2009
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES
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Issue Dt:
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09/07/2010
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12112611
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Filing Dt:
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04/30/2008
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Pub Dt:
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08/28/2008
| | | | |
Title:
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TRANSLATION DATA PREFETCH IN AN IOMMU
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Patent #:
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Issue Dt:
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12/03/2013
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12113064
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Filing Dt:
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04/30/2008
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Pub Dt:
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11/05/2009
| | | | |
Title:
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PENTACENE-CARBON NANOTUBE COMPOSITE, METHOD OF FORMING THE COMPOSITE, AND SEMICONDUCTOR DEVICE INCLUDING THE COMPOSITE
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Patent #:
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Issue Dt:
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08/19/2014
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12113230
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05/01/2008
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Pub Dt:
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11/05/2009
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Title:
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PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR PB-FREE C4 INTEGRATED CIRCUIT CHIP JOINING
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11/30/2010
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12113288
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05/01/2008
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Pub Dt:
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11/05/2009
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Title:
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METHODS OF OPTIMIZING TIMING OF SIGNALS IN AN INTEGRATED CIRCUIT DESIGN USING PROXY SLACK VALUES
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Issue Dt:
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02/22/2011
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12113374
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05/01/2008
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Pub Dt:
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11/05/2009
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Title:
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TEST PATTERN BASED PROCESS MODEL CALIBRATION
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06/28/2011
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12113457
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05/01/2008
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09/04/2008
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Title:
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METHOD FOR FACILITATING ACCESS TO ELECTRONIC COMPONENTS
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01/04/2011
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12113462
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05/01/2008
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Pub Dt:
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11/05/2009
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Title:
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HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS
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07/31/2012
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12113510
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05/01/2008
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11/05/2009
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Title:
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TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER
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02/15/2011
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12113559
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05/01/2008
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Pub Dt:
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11/05/2009
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Title:
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METHOD OF DETECTING REPEATING DEFECTS IN LITHOGRAPHY MASKS ON THE BASIS OF TEST SUBSTRATES EXPOSED UNDER VARYING CONDITIONS
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08/30/2011
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12113663
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05/01/2008
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11/05/2009
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COMPUTATIONAL DEVICE POWER-SAVINGS
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09/27/2011
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12114070
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05/02/2008
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06/18/2009
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Title:
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STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM
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07/21/2009
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12114145
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05/02/2008
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09/25/2008
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Title:
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CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS
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09/06/2011
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12114203
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05/02/2008
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Pub Dt:
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08/21/2008
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Title:
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SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS
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10/06/2009
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12114636
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05/02/2008
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10/02/2008
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Title:
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METHOD OF FABRICATING A MAGNETIC SHIFT REGISTER
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01/18/2011
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12114853
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05/05/2008
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Pub Dt:
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08/28/2008
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PROGRAMMABLE VOLTAGE DIVIDER
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11/09/2010
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12114857
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05/05/2008
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08/28/2008
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Title:
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DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS
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09/13/2011
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12115056
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05/05/2008
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11/05/2009
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Title:
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OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME
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11/16/2010
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12115065
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05/05/2008
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Pub Dt:
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08/28/2008
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Title:
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HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME
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02/15/2011
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12115166
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05/05/2008
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Pub Dt:
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12/31/2009
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Title:
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SYSTEMS FOR STRUCTURAL CLUSTERING OF TIME SEQUENCES
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Issue Dt:
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11/01/2011
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12115355
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05/05/2008
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Pub Dt:
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11/05/2009
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Title:
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TRANSIENT TRANSACTIONAL CACHE
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Patent #:
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Issue Dt:
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06/08/2010
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12115473
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05/05/2008
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Pub Dt:
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09/04/2008
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Title:
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SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION
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Patent #:
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Issue Dt:
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08/23/2011
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12115618
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05/06/2008
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Pub Dt:
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11/12/2009
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Title:
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METHOD AND APPARATUS OF WATER COOLING SEVERAL PARALLEL CIRCUIT CARDS EACH CONTAINING SEVERAL CHIP PACKAGES
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Patent #:
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Issue Dt:
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12/21/2010
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12115699
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05/06/2008
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Pub Dt:
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11/12/2009
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Title:
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CONDUCTIVE LINER AT AN INTERFACE BETWEEN A SHALLOW TRENCH ISOLATION STRUCTURE AND A BURIED OXIDE LAYER
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Issue Dt:
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05/17/2011
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12115731
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05/06/2008
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Pub Dt:
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08/28/2008
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Title:
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ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> SI UNDER BIAXIAL COMPRESSIVE STRAIN
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Patent #:
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Issue Dt:
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03/20/2012
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12115817
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05/06/2008
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Pub Dt:
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11/12/2009
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Title:
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REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY
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Patent #:
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Issue Dt:
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11/08/2011
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12116151
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Filing Dt:
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05/06/2008
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Pub Dt:
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08/28/2008
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Title:
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CLOCK AND DATA RECOVERY SYSTEM AND METHOD FOR CLOCK AND DATA RECOVERY BASED ON A FORWARD ERROR CORRECTION
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Issue Dt:
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06/05/2012
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12116317
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Filing Dt:
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05/07/2008
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10/02/2008
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Title:
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METHOD OF FORMING A LAND GRID ARRAY (LGA) INTERPOSER
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Issue Dt:
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05/15/2012
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12116470
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Filing Dt:
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05/07/2008
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Pub Dt:
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11/12/2009
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Title:
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AN ELECTRICAL CONTACT STRUCTURE HAVING MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER.
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Patent #:
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Issue Dt:
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06/23/2009
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12116626
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Filing Dt:
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05/07/2008
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Title:
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METHODS INVOLVING SILICON-ON-INSULATOR TRENCH MEMORY WITH IMPLANTED PLATE
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Issue Dt:
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10/18/2011
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12116655
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Filing Dt:
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05/07/2008
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Pub Dt:
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12/11/2008
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Title:
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METHOD OF FORMING A FLIP-CHIP PACKAGE
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Issue Dt:
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07/26/2011
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12116771
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05/07/2008
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Pub Dt:
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08/28/2008
| | | | |
Title:
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METHOD FOR ACHIEVING VERY HIGH BANDWIDTH BETWEEN THE LEVELS OF A CACHE HIERARCHY IN 3-DIMENSIONAL STRUCTURES, AND A 3-DIMENSIONAL STRUCTURE RESULTING THEREFROM
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Issue Dt:
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03/02/2010
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12117098
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Filing Dt:
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05/08/2008
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Pub Dt:
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10/02/2008
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Title:
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SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER AND METHOD
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Issue Dt:
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02/01/2011
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12117784
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05/09/2008
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Pub Dt:
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11/12/2009
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Title:
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CIRCUIT AND METHOD USING DISTRIBUTED PHASE CHANGE ELEMENTS FOR ACROSS-CHIP TEMPERATURE PROFILING
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Issue Dt:
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02/08/2011
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Application #:
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12117803
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Filing Dt:
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05/09/2008
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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INTERCONNECTING (MAPPING) A TWO-DIMENSIONAL OPTOELECTRONIC (OE) DEVICE ARRAY TO A ONE-DIMENSIONAL WAVEGUIDE ARRAY
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Patent #:
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Issue Dt:
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01/11/2011
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12117841
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Filing Dt:
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05/09/2008
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Pub Dt:
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09/04/2008
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Title:
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SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP
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Patent #:
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Issue Dt:
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03/17/2009
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Application #:
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12118441
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Filing Dt:
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05/09/2008
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Title:
|
SYSTEMS INVOLVING SPIN-TRANSFER MAGNETIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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12118496
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Filing Dt:
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05/09/2008
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Title:
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METHODS INVOLVING RESETTING SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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12118776
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Filing Dt:
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05/12/2008
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Publication #:
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Pub Dt:
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10/09/2008
| | | | |
Title:
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POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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12118818
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Filing Dt:
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05/12/2008
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Publication #:
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Pub Dt:
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09/04/2008
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Title:
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METHOD AND APPARATUS FOR FILTERING MEMORY WRITE SNOOP ACTIVITY IN A DISTRIBUTED SHARED MEMORY COMPUTER
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12118875
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Filing Dt:
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05/12/2008
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Publication #:
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Pub Dt:
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10/16/2008
| | | | |
Title:
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STRUCTURE FOR LOW CAPACITANCE ESD ROBUST DIODES
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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12119042
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Filing Dt:
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05/12/2008
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Publication #:
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Pub Dt:
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02/05/2009
| | | | |
Title:
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METHOD AND SYSTEM FOR SCHEDULING A STREAM OF PRODUCTS IN A MANUFACTURING ENVIRONMENT BY USING PROCESS-SPECIFIC WIP LIMITS
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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12119384
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Filing Dt:
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05/12/2008
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Publication #:
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Pub Dt:
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11/12/2009
| | | | |
Title:
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METHOD OF FORMING STEPPED RECESSES FOR EMBEDDED STRAIN ELEMENTS IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12119526
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Filing Dt:
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05/13/2008
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Publication #:
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Pub Dt:
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11/19/2009
| | | | |
Title:
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METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR
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Patent #:
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Issue Dt:
|
06/14/2011
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Application #:
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12119765
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Filing Dt:
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05/13/2008
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Publication #:
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Pub Dt:
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10/09/2008
| | | | |
Title:
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SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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12119924
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Filing Dt:
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05/13/2008
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Publication #:
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Pub Dt:
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11/19/2009
| | | | |
Title:
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PROGRAMMABLE DIRECT MEMORY ACCESS CONTROLLER HAVING PIPELINED AND SEQUENTIALLY CONNECTED STAGES
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|
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Patent #:
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Issue Dt:
|
09/18/2012
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Application #:
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12119975
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Filing Dt:
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05/13/2008
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Publication #:
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Pub Dt:
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11/19/2009
| | | | |
Title:
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CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS
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Patent #:
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Issue Dt:
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02/14/2012
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Application #:
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12120029
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Filing Dt:
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05/13/2008
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Publication #:
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Pub Dt:
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11/19/2009
| | | | |
Title:
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SEMICONDUCTOR PACKAGE STRUCTURES HAVING LIQUID COOLERS INTEGRATED WITH FIRST LEVEL CHIP PACKAGE MODULES
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|
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Patent #:
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Issue Dt:
|
10/18/2011
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Application #:
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12120286
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Filing Dt:
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05/14/2008
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
Title:
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OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS
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|
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Patent #:
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Issue Dt:
|
04/19/2011
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Application #:
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12120455
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Filing Dt:
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05/14/2008
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Publication #:
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Pub Dt:
|
09/04/2008
| | | | |
Title:
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METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS
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|
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Patent #:
|
|
Issue Dt:
|
01/04/2011
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Application #:
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12120658
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
11/19/2009
| | | | |
Title:
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FABRICATION OF A CMOS STRUCTURE WITH A HIGH-K DIELECTRIC LAYER OXIDIZING AN ALUMINUM LAYER IN PFET REGION
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|
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Patent #:
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|
Issue Dt:
|
03/27/2012
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Application #:
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12120701
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
09/04/2008
| | | | |
Title:
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DESIGN STRUCTURES FOR SEMICONDUCTOR STRUCTURES WITH ERROR DETECTION AND CORRECTION
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|
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Patent #:
|
|
Issue Dt:
|
05/03/2011
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Application #:
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12120836
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
11/19/2009
| | | | |
Title:
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REDUCED FLOATING BODY EFFECT WITHOUT IMPACT ON PERFORMANCE-ENHANCING STRESS
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|
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Patent #:
|
|
Issue Dt:
|
02/28/2012
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Application #:
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12120854
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Filing Dt:
|
05/15/2008
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Publication #:
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Pub Dt:
|
10/09/2008
| | | | |
Title:
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REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SIGE CONTAINING SUBSTRATES
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|
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Patent #:
|
|
Issue Dt:
|
11/08/2011
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Application #:
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12120899
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
08/28/2008
| | | | |
Title:
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THREE-DIMENSIONAL CASCADED POWER DISTRIBUTION IN A SEMICONDUCTOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
05/03/2011
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Application #:
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12121292
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
11/19/2009
| | | | |
Title:
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PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS
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|
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Patent #:
|
|
Issue Dt:
|
12/30/2008
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Application #:
|
12121378
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Filing Dt:
|
05/15/2008
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Title:
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DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION
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|
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Patent #:
|
|
Issue Dt:
|
08/30/2011
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Application #:
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12121397
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Filing Dt:
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05/15/2008
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Publication #:
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|
Pub Dt:
|
12/04/2008
| | | | |
Title:
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METHOD AND SYSTEM FOR PLACEMENT OF ELECTRIC CIRCUIT COMPONENTS IN INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
|
|
Issue Dt:
|
01/11/2011
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Application #:
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12121468
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
11/13/2008
| | | | |
Title:
|
METHODS FOR FORMING CO-PLANAR WAFER-SCALE CHIP PACKAGES
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|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
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Application #:
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12121689
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
11/20/2008
| | | | |
Title:
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FIREWALL FOR CONTROLLING CONNECTIONS BETWEEN A CLIENT MACHINE AND A NETWORK
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|
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Patent #:
|
|
Issue Dt:
|
10/12/2010
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Application #:
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12121875
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Filing Dt:
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05/16/2008
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Publication #:
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Pub Dt:
|
11/19/2009
| | | | |
Title:
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PROCESS FOR PCM INTEGRATION WITH POLY-EMITTER BJT AS ACCESS DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
01/04/2011
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Application #:
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12121962
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Filing Dt:
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05/16/2008
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Publication #:
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|
Pub Dt:
|
10/16/2008
| | | | |
Title:
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PROBABILISTIC REGRESSION SUITES FOR FUNCTIONAL VERIFICATION
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|
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Patent #:
|
|
Issue Dt:
|
06/28/2011
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Application #:
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12122227
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Filing Dt:
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05/16/2008
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Publication #:
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Pub Dt:
|
09/11/2008
| | | | |
Title:
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HIGHER PERFORMANCE CMOS ON (110) WAFERS
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|
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Patent #:
|
|
Issue Dt:
|
06/21/2011
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Application #:
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12122259
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Filing Dt:
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05/16/2008
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Publication #:
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Pub Dt:
|
12/04/2008
| | | | |
Title:
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METHOD AND SYSTEM FOR ROUTING OF INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
|
|
Issue Dt:
|
01/11/2011
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Application #:
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12122451
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Filing Dt:
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05/16/2008
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Publication #:
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Pub Dt:
|
09/04/2008
| | | | |
Title:
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SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
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|
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Patent #:
|
|
Issue Dt:
|
11/30/2010
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Application #:
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12122754
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Filing Dt:
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05/19/2008
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Publication #:
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Pub Dt:
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11/19/2009
| | | | |
Title:
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DESIGN STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS
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|
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Patent #:
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Issue Dt:
|
08/16/2011
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Application #:
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12122785
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Filing Dt:
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05/19/2008
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Publication #:
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Pub Dt:
|
11/19/2009
| | | | |
Title:
|
METHOD FOR CIRCUIT DESIGN
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|
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Patent #:
|
|
Issue Dt:
|
10/18/2011
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Application #:
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12122788
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Filing Dt:
|
05/19/2008
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Publication #:
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Pub Dt:
|
09/11/2008
| | | | |
Title:
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ASYMMETRICALLY STRESSED CMOS FINFET
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|
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Patent #:
|
|
Issue Dt:
|
06/02/2015
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Application #:
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12122929
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Filing Dt:
|
05/19/2008
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Publication #:
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Pub Dt:
|
11/19/2009
| | | | |
Title:
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METHOD FOR MONITORING FOCUS ON AN INTEGRATED WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
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Application #:
|
12122969
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Filing Dt:
|
05/19/2008
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Publication #:
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Pub Dt:
|
09/04/2008
| | | | |
Title:
|
THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
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|
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Patent #:
|
|
Issue Dt:
|
05/31/2011
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Application #:
|
12122981
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Filing Dt:
|
05/19/2008
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Publication #:
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Pub Dt:
|
05/07/2009
| | | | |
Title:
|
SELECTIVE PLACEMENT OF CARBON NANOTUBES ON OXIDE SURFACES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
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Application #:
|
12122984
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Filing Dt:
|
05/19/2008
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Publication #:
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Pub Dt:
|
09/04/2008
| | | | |
Title:
|
METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION
|
|
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Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
12123487
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Filing Dt:
|
05/20/2008
|
Title:
|
METHOD FOR EXTENDING LIFETIME RELIABILITY OF DIGITAL LOGIC DEVICES THROUGH REVERSAL OF AGING MECHANISMS
|
|
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Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12123524
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Filing Dt:
|
05/20/2008
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Publication #:
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Pub Dt:
|
06/04/2009
| | | | |
Title:
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METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS
|
|
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Patent #:
|
|
Issue Dt:
|
07/24/2012
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Application #:
|
12123735
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Filing Dt:
|
05/20/2008
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
|
SWITCH WITH REDUCED INSERTION LOSS
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|
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Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12123799
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Filing Dt:
|
05/20/2008
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Publication #:
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Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD OF FORMING AN EMBEDDED BARRIER LAYER FOR PROTECTION FROM CHEMICAL MECHANICAL POLISHING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12124106
|
Filing Dt:
|
05/20/2008
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Publication #:
|
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Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHOD AND ARRANGEMENTS FOR LINK POWER REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12124472
|
Filing Dt:
|
05/21/2008
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Publication #:
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Pub Dt:
|
11/26/2009
| | | | |
Title:
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PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12124551
|
Filing Dt:
|
05/21/2008
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Publication #:
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Pub Dt:
|
03/12/2009
| | | | |
Title:
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METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12125106
|
Filing Dt:
|
05/22/2008
|
Publication #:
|
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Pub Dt:
|
09/11/2008
| | | | |
Title:
|
DUAL STRESS STI
|
|