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09/16/2010
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03/03/2011
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03/03/2011
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03/03/2011
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03/03/2011
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03/03/2011
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11/19/2013
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12/24/2009
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03/27/2012
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12/31/2009
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03/03/2011
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03/03/2011
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03/03/2011
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03/03/2011
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02/05/2013
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03/03/2011
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07/19/2016
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03/03/2011
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08/07/2012
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09/02/2009
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09/23/2010
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04/17/2012
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04/01/2010
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07/30/2013
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09/02/2009
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09/16/2010
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01/29/2013
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03/03/2011
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08/19/2014
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03/03/2011
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Method of Making an Electronic Package
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09/13/2011
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12552548
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04/01/2010
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08/23/2011
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09/02/2009
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09/23/2010
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10/18/2011
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09/03/2009
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03/03/2011
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11/06/2012
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09/03/2009
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03/03/2011
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09/30/2010
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VARIABLE DYNAMIC RANGE PIXEL SENSOR CELL, DESIGN STRUCTURE AND METHOD
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02/24/2015
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09/03/2009
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04/01/2010
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05/15/2012
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09/03/2009
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01/21/2010
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01/08/2013
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09/04/2009
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03/10/2011
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04/05/2011
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09/04/2009
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12/31/2009
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02/14/2012
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09/08/2009
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12/31/2009
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ELECTRICAL ANTIFUSE
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05/15/2012
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09/08/2009
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03/10/2011
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08/07/2012
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09/08/2009
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12/31/2009
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03/20/2012
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09/09/2009
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04/01/2010
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03/13/2012
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09/09/2009
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03/10/2011
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12/18/2012
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09/09/2009
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03/10/2011
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01/31/2012
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09/09/2009
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03/10/2011
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12/07/2010
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09/09/2009
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12/31/2009
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HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME
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04/12/2011
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12556335
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09/09/2009
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09/02/2010
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03/01/2011
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09/10/2009
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03/10/2011
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10/16/2012
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09/10/2009
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03/10/2011
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02/22/2011
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09/10/2009
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03/10/2011
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08/23/2011
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09/11/2009
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01/07/2010
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12/04/2012
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09/11/2009
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03/17/2011
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07/31/2012
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09/14/2009
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03/17/2011
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11/23/2010
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09/14/2009
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07/26/2011
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09/14/2009
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03/17/2011
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03/20/2012
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09/15/2009
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03/17/2011
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ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE
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10/04/2011
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09/15/2009
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03/17/2011
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DEVICE AND METHOD FOR PROVIDING AN INTEGRATED CIRCUIT WITH A UNIQUE INDENTIFICATION
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07/09/2013
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09/16/2009
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03/17/2011
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04/05/2011
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09/16/2009
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03/17/2011
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DELAY CIRCUIT WITH DELAY EQUAL TO PERCENTAGE OF INPUT PULSE WIDTH
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06/07/2011
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09/16/2009
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03/17/2011
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12/27/2011
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09/16/2009
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03/17/2011
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03/20/2012
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09/17/2009
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03/17/2011
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02/21/2012
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09/17/2009
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03/17/2011
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02/21/2012
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09/17/2009
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03/17/2011
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08/14/2012
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09/17/2009
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03/17/2011
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11/08/2011
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09/17/2009
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05/06/2010
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07/31/2012
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12561704
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09/17/2009
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03/17/2011
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11/01/2011
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12561708
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09/17/2009
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03/17/2011
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METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION
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05/14/2013
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12561827
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09/17/2009
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01/14/2010
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BEOL COMPATIBLE FET STRUCTURE
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05/24/2011
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12561880
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09/17/2009
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03/17/2011
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07/31/2012
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12562222
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09/18/2009
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03/24/2011
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DOUBLE PATTERNING PROCESS FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING
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02/01/2011
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12562262
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09/18/2009
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01/14/2010
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VIRTUALIZING AN IOMMU
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04/17/2012
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12562419
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09/18/2009
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03/24/2011
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METHOD OF FABRICATING A TRENCH-GENERATED TRANSISTOR STRUCTURE
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12/11/2012
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12562540
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09/18/2009
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03/24/2011
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SYSTEM TO REDUCE THE TIME AND COMPLEXITY OF SELF CONFIGURING SYSTEMS
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10/22/2013
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12562556
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09/18/2009
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05/06/2010
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METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MICROELECTRONIC MANUFACTURING TECHNIQUES
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08/27/2013
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12562659
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09/18/2009
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03/24/2011
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Title:
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METHOD TO COMPUTE WAIT TIME
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02/09/2016
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12562849
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09/18/2009
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03/24/2011
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Title:
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SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES
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07/26/2011
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12562873
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09/18/2009
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03/24/2011
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METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTIVE RESISTOR STRUCTURE
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09/25/2012
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12563021
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09/18/2009
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03/24/2011
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AUTOMATIC POSITIONING OF GATE ARRAY CIRCUITS IN AN INTEGRATED CIRCUIT DESIGN
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10/30/2012
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12563032
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09/18/2009
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03/24/2011
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METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SIGE
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02/15/2011
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12563183
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09/21/2009
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Title:
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06/25/2013
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12563186
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09/21/2009
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03/24/2011
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MEMORY LEAK MONITORING SYSTEM AND ASSOCIATED METHODS
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02/28/2012
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12563553
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09/21/2009
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03/24/2011
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LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES
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06/28/2011
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12563610
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09/21/2009
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03/24/2011
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BIDIRECTIONAL ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS
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09/18/2012
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12564061
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09/22/2009
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03/24/2011
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METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES
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08/07/2012
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12564482
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09/22/2009
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01/14/2010
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02/15/2011
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12564570
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09/22/2009
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Title:
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05/28/2013
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12564996
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09/23/2009
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03/24/2011
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THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
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06/12/2012
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12565020
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09/23/2009
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05/06/2010
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STRESS TRANSFER ENHANCEMENT IN TRANSISTORS BY A LATE GATE RE-CRYSTALLIZATION
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05/29/2012
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12565802
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09/24/2009
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03/24/2011
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MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
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09/20/2011
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12566004
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09/24/2009
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03/24/2011
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HIGH-PERFORMANCE FETS WITH EMBEDDED STRESSORS
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06/23/2015
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12566255
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09/24/2009
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03/24/2011
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Parallel Processing of ETL Jobs Involving Extensible Markup Language Documents
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02/28/2012
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12566430
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09/24/2009
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03/24/2011
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ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES
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06/05/2012
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12566717
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09/25/2009
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03/31/2011
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ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL
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12/25/2012
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12566862
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09/25/2009
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03/31/2011
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DUAL BETA RATIO SRAM
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08/14/2012
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12566870
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09/25/2009
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03/31/2011
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ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION
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05/24/2011
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12567279
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09/25/2009
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02/04/2010
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APPARATUS AND METHOD FOR REMOVING BUBBLES FROM A PROCESS LIQUID
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09/13/2011
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12567490
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09/25/2009
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01/21/2010
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INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM
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05/15/2012
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12567963
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09/28/2009
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03/31/2011
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REPLACEMENT SPACER FOR TUNNEL FETS
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07/24/2012
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12568035
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09/28/2009
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03/31/2011
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WRITING TO MEMORY USING ADAPTIVE WRITE TECHNIQUES
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07/31/2012
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12568083
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09/28/2009
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03/31/2011
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TOOL COMMONALITY AND STRATIFICATION ANALYSIS TO ENHANCE A PRODUCTION PROCESS
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08/07/2012
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12568287
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09/28/2009
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03/31/2011
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SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE
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08/07/2012
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12568985
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09/29/2009
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03/31/2011
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SYSTEM AND METHOD FOR ESTIMATING LEAKAGE CURRENT OF AN ELECTRONIC CIRCUIT
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03/13/2012
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12569077
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09/29/2009
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01/21/2010
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METHODS FOR FORMING DENSE DIELECTRIC LAYER OVER POROUS DIELECTRICS
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06/19/2012
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12569200
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09/29/2009
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03/31/2011
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PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION
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12/18/2012
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12569421
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09/29/2009
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03/31/2011
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CHARACTERIZATION OF LONG RANGE VARIABILITY
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03/27/2012
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12570333
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09/30/2009
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03/31/2011
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BUSINESS PROCESS ERROR HANDLING THROUGH PROCESS INSTANCE BACKUP AND RECOVERY
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12/27/2011
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12570384
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09/30/2009
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03/31/2011
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ENHANCED STRESS-RETENTION FIN-FET DEVICES AND METHODS OF FABRICATING ENHANCED STRESS RETENTION FIN-FET DEVICES
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07/31/2012
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12570415
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09/30/2009
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03/31/2011
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METHOD OF GENERATING UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE
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08/07/2012
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12570418
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09/30/2009
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03/31/2011
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Title:
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METHOD FOR CALCULATING CAPACITANCE GRADIENTS IN VLSI LAYOUTS USING A SHAPE PROCESSING ENGINE
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