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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 67 of 146
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1
Patent #:
8337627
Issue Dt:
12/25/2012
Application #:
12571477
Filing Dt:
10/01/2009
Publication #:
US20110079255
Pub Dt:
04/07/2011
Title:
CLEANING EXHAUST SCREENS IN A MANUFACTURING PROCESS
2
Patent #:
8230378
Issue Dt:
07/24/2012
Application #:
12572297
Filing Dt:
10/02/2009
Publication #:
US20100023913
Pub Dt:
01/28/2010
Title:
METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING
3
Patent #:
8993428
Issue Dt:
03/31/2015
Application #:
12573188
Filing Dt:
10/05/2009
Publication #:
US20110079827
Pub Dt:
04/07/2011
Title:
STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION
4
Patent #:
7867897
Issue Dt:
01/11/2011
Application #:
12573407
Filing Dt:
10/05/2009
Publication #:
US20100021656
Pub Dt:
01/28/2010
Title:
LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION
5
Patent #:
8546252
Issue Dt:
10/01/2013
Application #:
12573440
Filing Dt:
10/05/2009
Publication #:
US20110079828
Pub Dt:
04/07/2011
Title:
METAL GATE FET HAVING REDUCED THRESHOLD VOLTAGE ROLL-OFF
6
Patent #:
7927895
Issue Dt:
04/19/2011
Application #:
12574118
Filing Dt:
10/06/2009
Publication #:
US20110080180
Pub Dt:
04/07/2011
Title:
VARYING CAPACITANCE VOLTAGE CONTRAST STRUCTURES TO DETERMINE DEFECT RESISTANCE
7
Patent #:
8680617
Issue Dt:
03/25/2014
Application #:
12574126
Filing Dt:
10/06/2009
Publication #:
US20110079851
Pub Dt:
04/07/2011
Title:
SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS
8
Patent #:
8946028
Issue Dt:
02/03/2015
Application #:
12574296
Filing Dt:
10/06/2009
Publication #:
US20110079855
Pub Dt:
04/07/2011
Title:
MERGED FINFETS AND METHOD OF MANUFACTURING THE SAME
9
Patent #:
7943458
Issue Dt:
05/17/2011
Application #:
12574318
Filing Dt:
10/06/2009
Publication #:
US20110081754
Pub Dt:
04/07/2011
Title:
METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING
10
Patent #:
8125048
Issue Dt:
02/28/2012
Application #:
12574926
Filing Dt:
10/07/2009
Publication #:
US20110079874
Pub Dt:
04/07/2011
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
11
Patent #:
8367430
Issue Dt:
02/05/2013
Application #:
12575068
Filing Dt:
10/07/2009
Publication #:
US20110079779
Pub Dt:
04/07/2011
Title:
SHAPE CHARACTERIZATION WITH ELLIPTIC FOURIER DESCRIPTOR FOR CONTACT OR ANY CLOSED STRUCTURES ON THE CHIP
12
Patent #:
8101486
Issue Dt:
01/24/2012
Application #:
12575344
Filing Dt:
10/07/2009
Publication #:
US20110081764
Pub Dt:
04/07/2011
Title:
METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
13
Patent #:
8389663
Issue Dt:
03/05/2013
Application #:
12575515
Filing Dt:
10/08/2009
Publication #:
US20110083887
Pub Dt:
04/14/2011
Title:
PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
14
Patent #:
8138523
Issue Dt:
03/20/2012
Application #:
12575962
Filing Dt:
10/08/2009
Publication #:
US20110084315
Pub Dt:
04/14/2011
Title:
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
15
Patent #:
8482132
Issue Dt:
07/09/2013
Application #:
12575980
Filing Dt:
10/08/2009
Publication #:
US20110084403
Pub Dt:
04/14/2011
Title:
PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT
16
Patent #:
8143135
Issue Dt:
03/27/2012
Application #:
12575989
Filing Dt:
10/08/2009
Publication #:
US20110084360
Pub Dt:
04/14/2011
Title:
EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
17
Patent #:
8130525
Issue Dt:
03/06/2012
Application #:
12576275
Filing Dt:
10/09/2009
Publication #:
US20110088005
Pub Dt:
04/14/2011
Title:
METHOD AND APPARATUS FOR CONFIGURING A CONTENT-ADDRESSABLE MEMORY (CAM) DESIGN AS BINARY CAM OR TERNARY CAM
18
Patent #:
8538129
Issue Dt:
09/17/2013
Application #:
12576597
Filing Dt:
10/09/2009
Publication #:
US20110085723
Pub Dt:
04/14/2011
Title:
MASK PROGRAM DEFECT TEST
19
Patent #:
8030144
Issue Dt:
10/04/2011
Application #:
12576987
Filing Dt:
10/09/2009
Publication #:
US20110084336
Pub Dt:
04/14/2011
Title:
SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS, AND RELATED FABRICATION METHODS
20
Patent #:
8288657
Issue Dt:
10/16/2012
Application #:
12577259
Filing Dt:
10/12/2009
Publication #:
US20110083888
Pub Dt:
04/14/2011
Title:
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
21
Patent #:
8278165
Issue Dt:
10/02/2012
Application #:
12577628
Filing Dt:
10/12/2009
Publication #:
US20110086495
Pub Dt:
04/14/2011
Title:
METHODS FOR PROTECTING FILM LAYERS WHILE REMOVING HARDMASKS DURING FABRICATION OF SEMICONDUCTOR DEVICES
22
Patent #:
8082464
Issue Dt:
12/20/2011
Application #:
12578372
Filing Dt:
10/13/2009
Publication #:
US20110087919
Pub Dt:
04/14/2011
Title:
MANAGING AVAILABILITY OF A COMPONENT HAVING A CLOSED ADDRESS SPACE
23
Patent #:
8218378
Issue Dt:
07/10/2012
Application #:
12579089
Filing Dt:
10/14/2009
Publication #:
US20110085390
Pub Dt:
04/14/2011
Title:
WORD-LINE LEVEL SHIFT CIRCUIT
24
Patent #:
8538740
Issue Dt:
09/17/2013
Application #:
12579124
Filing Dt:
10/14/2009
Publication #:
US20110087469
Pub Dt:
04/14/2011
Title:
REAL-TIME PERFORMANCE MODELING OF SOFTWARE SYSTEMS WITH MULTI-CLASS WORKLOAD
25
Patent #:
8241927
Issue Dt:
08/14/2012
Application #:
12579216
Filing Dt:
10/14/2009
Publication #:
US20110086445
Pub Dt:
04/14/2011
Title:
METHODS RELATING TO CAPACITIVE MONITORING OF LAYER CHARACTERISTICS DURING BACK END-OF-THE-LINE PROCESSING
26
Patent #:
8296256
Issue Dt:
10/23/2012
Application #:
12579442
Filing Dt:
10/15/2009
Publication #:
US20110093431
Pub Dt:
04/21/2011
Title:
SAT-BASED SYNTHESIS OF A CLOCK GATING FUNCTION
27
Patent #:
8268679
Issue Dt:
09/18/2012
Application #:
12579654
Filing Dt:
10/15/2009
Publication #:
US20100107403
Pub Dt:
05/06/2010
Title:
SEMICONDUCTOR DEVICE COMPRISING EFUSES OF ENHANCED PROGRAMMING EFFICIENCY
28
Patent #:
8327302
Issue Dt:
12/04/2012
Application #:
12580330
Filing Dt:
10/16/2009
Publication #:
US20110093825
Pub Dt:
04/21/2011
Title:
TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC
29
Patent #:
8233337
Issue Dt:
07/31/2012
Application #:
12581440
Filing Dt:
10/19/2009
Publication #:
US20110090750
Pub Dt:
04/21/2011
Title:
SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS
30
Patent #:
8034692
Issue Dt:
10/11/2011
Application #:
12581924
Filing Dt:
10/20/2009
Publication #:
US20110089499
Pub Dt:
04/21/2011
Title:
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
31
Patent #:
8288222
Issue Dt:
10/16/2012
Application #:
12582139
Filing Dt:
10/20/2009
Publication #:
US20110089495
Pub Dt:
04/21/2011
Title:
APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS
32
Patent #:
8198396
Issue Dt:
06/12/2012
Application #:
12583030
Filing Dt:
08/12/2009
Publication #:
US20090304908
Pub Dt:
12/10/2009
Title:
METHODS OF FABRICATING PLASTICIZED, ANTIPLASTICIZED AND CRYSTALLINE CONDUCTING POLYMERS AND PRECURSORS THEREOF
33
Patent #:
8076703
Issue Dt:
12/13/2011
Application #:
12603353
Filing Dt:
10/21/2009
Publication #:
US20100044761
Pub Dt:
02/25/2010
Title:
SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME
34
Patent #:
8298459
Issue Dt:
10/30/2012
Application #:
12603567
Filing Dt:
10/21/2009
Publication #:
US20110089589
Pub Dt:
04/21/2011
Title:
SPIN-MOUNTED FABRICATION OF INJECTION MOLDED MICRO-OPTICS
35
Patent #:
8102599
Issue Dt:
01/24/2012
Application #:
12603569
Filing Dt:
10/21/2009
Publication #:
US20110090570
Pub Dt:
04/21/2011
Title:
FABRICATION OF OPTICAL FILTERS INTEGRATED WITH INJECTION MOLDED MICROLENSES
36
Patent #:
9018024
Issue Dt:
04/28/2015
Application #:
12603668
Filing Dt:
10/22/2009
Publication #:
US20110095393
Pub Dt:
04/28/2011
Title:
CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS
37
Patent #:
8124427
Issue Dt:
02/28/2012
Application #:
12603671
Filing Dt:
10/22/2009
Publication #:
US20110097824
Pub Dt:
04/28/2011
Title:
METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON- INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
38
Patent #:
8301290
Issue Dt:
10/30/2012
Application #:
12603679
Filing Dt:
10/22/2009
Publication #:
US20110098838
Pub Dt:
04/28/2011
Title:
SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS
39
Patent #:
8110483
Issue Dt:
02/07/2012
Application #:
12603737
Filing Dt:
10/22/2009
Publication #:
US20110095366
Pub Dt:
04/28/2011
Title:
FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER
40
Patent #:
8207027
Issue Dt:
06/26/2012
Application #:
12603838
Filing Dt:
10/22/2009
Publication #:
US20100041198
Pub Dt:
02/18/2010
Title:
TRIPLE GATE AND DOUBLE GATE FINFETS WITH DIFFERENT VERTICAL DIMENSION FINS
41
Patent #:
7932143
Issue Dt:
04/26/2011
Application #:
12604281
Filing Dt:
10/22/2009
Publication #:
US20110095341
Pub Dt:
04/28/2011
Title:
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS
42
Patent #:
7954021
Issue Dt:
05/31/2011
Application #:
12604614
Filing Dt:
10/23/2009
Publication #:
US20110099419
Pub Dt:
04/28/2011
Title:
SOLID STATE DRIVE WITH FLASH SPARING
43
Patent #:
8883610
Issue Dt:
11/11/2014
Application #:
12604703
Filing Dt:
10/23/2009
Publication #:
US20100133648
Pub Dt:
06/03/2010
Title:
MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES
44
Patent #:
8407633
Issue Dt:
03/26/2013
Application #:
12605417
Filing Dt:
10/26/2009
Publication #:
US20110099527
Pub Dt:
04/28/2011
Title:
DYNAMICALLY RECONFIGURABLE SELF-MONITORING CIRCUIT
45
Patent #:
8614492
Issue Dt:
12/24/2013
Application #:
12605523
Filing Dt:
10/26/2009
Publication #:
US20110095267
Pub Dt:
04/28/2011
Title:
NANOWIRE STRESS SENSORS, STRESS SENSOR INTEGRATED CIRCUITS, AND DESIGN STRUCTURES FOR A STRESS SENSOR INTEGRATED CIRCUIT
46
Patent #:
8035141
Issue Dt:
10/11/2011
Application #:
12607104
Filing Dt:
10/28/2009
Publication #:
US20110095343
Pub Dt:
04/28/2011
Title:
BI-LAYER NFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT
47
Patent #:
8120058
Issue Dt:
02/21/2012
Application #:
12607116
Filing Dt:
10/28/2009
Publication #:
US20110095333
Pub Dt:
04/28/2011
Title:
HIGH-DRIVE CURRENT MOSFET
48
Patent #:
8307994
Issue Dt:
11/13/2012
Application #:
12607258
Filing Dt:
10/28/2009
Publication #:
US20110094884
Pub Dt:
04/28/2011
Title:
SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION
49
Patent #:
8159060
Issue Dt:
04/17/2012
Application #:
12608368
Filing Dt:
10/29/2009
Publication #:
US20110101537
Pub Dt:
05/05/2011
Title:
HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION
50
Patent #:
8232196
Issue Dt:
07/31/2012
Application #:
12608377
Filing Dt:
10/29/2009
Publication #:
US20110100697
Pub Dt:
05/05/2011
Title:
INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
51
Patent #:
7961996
Issue Dt:
06/14/2011
Application #:
12608518
Filing Dt:
10/29/2009
Publication #:
US20100046883
Pub Dt:
02/25/2010
Title:
COUPLING DEVICE FOR USE IN OPTICAL WAVEGUIDES
52
Patent #:
8340939
Issue Dt:
12/25/2012
Application #:
12610090
Filing Dt:
10/30/2009
Publication #:
US20110106483
Pub Dt:
05/05/2011
Title:
METHOD AND APPARATUS FOR SELECTING PATHS FOR USE IN AT-SPEED TESTING
53
Patent #:
8781792
Issue Dt:
07/15/2014
Application #:
12610291
Filing Dt:
10/31/2009
Publication #:
US20110106497
Pub Dt:
05/05/2011
Title:
Yield Computation and Optimization for Selective Voltage Binning
54
Patent #:
7932134
Issue Dt:
04/26/2011
Application #:
12610563
Filing Dt:
11/02/2009
Publication #:
US20100047972
Pub Dt:
02/25/2010
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
55
Patent #:
8354351
Issue Dt:
01/15/2013
Application #:
12610630
Filing Dt:
11/02/2009
Publication #:
US20100044592
Pub Dt:
02/25/2010
Title:
SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES
56
Patent #:
8288271
Issue Dt:
10/16/2012
Application #:
12610679
Filing Dt:
11/02/2009
Publication #:
US20110101507
Pub Dt:
05/05/2011
Title:
METHOD FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
57
Patent #:
8298751
Issue Dt:
10/30/2012
Application #:
12611043
Filing Dt:
11/02/2009
Publication #:
US20110104900
Pub Dt:
05/05/2011
Title:
ALKALINE RINSE AGENTS FOR USE IN LITHOGRAPHIC PATTERNING
58
Patent #:
8614435
Issue Dt:
12/24/2013
Application #:
12611421
Filing Dt:
11/03/2009
Publication #:
US20110101308
Pub Dt:
05/05/2011
Title:
UTILIZATION OF ORGANIC BUFFER LAYER TO FABRICATE HIGH PERFORMANCE CARBON NANOELECTRONIC DEVICES
59
Patent #:
8210741
Issue Dt:
07/03/2012
Application #:
12611519
Filing Dt:
11/03/2009
Publication #:
US20100046574
Pub Dt:
02/25/2010
Title:
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
60
Patent #:
8689180
Issue Dt:
04/01/2014
Application #:
12611561
Filing Dt:
11/03/2009
Publication #:
US20110107297
Pub Dt:
05/05/2011
Title:
SYSTEMS AND METHODS FOR RESOURCE LEAK DETECTION
61
Patent #:
8021971
Issue Dt:
09/20/2011
Application #:
12611946
Filing Dt:
11/04/2009
Publication #:
US20110101472
Pub Dt:
05/05/2011
Title:
STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS
62
Patent #:
8514374
Issue Dt:
08/20/2013
Application #:
12611947
Filing Dt:
11/04/2009
Publication #:
US20110102760
Pub Dt:
05/05/2011
Title:
ALIGNMENT METHOD FOR SEMICONDUCTOR PROCESSING
63
Patent #:
8105928
Issue Dt:
01/31/2012
Application #:
12612018
Filing Dt:
11/04/2009
Publication #:
US20110101309
Pub Dt:
05/05/2011
Title:
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
64
Patent #:
8679906
Issue Dt:
03/25/2014
Application #:
12612035
Filing Dt:
11/04/2009
Publication #:
US20100044794
Pub Dt:
02/25/2010
Title:
ASYMMETRIC MULTI-GATED TRANSISTOR AND METHOD FOR FORMING
65
Patent #:
8168449
Issue Dt:
05/01/2012
Application #:
12612258
Filing Dt:
11/04/2009
Publication #:
US20110104827
Pub Dt:
05/05/2011
Title:
TEMPLATE-REGISTERED DIBLOCK COPOLYMER MASK FOR MRAM DEVICE FORMATION
66
Patent #:
9047144
Issue Dt:
06/02/2015
Application #:
12612624
Filing Dt:
11/04/2009
Publication #:
US20110107354
Pub Dt:
05/05/2011
Title:
SYSTEM AND METHOD FOR PROVIDING QUALITY-OF-SERVICES IN A MULTI-EVENT PROCESSING ENVIRONMENT
67
Patent #:
7829427
Issue Dt:
11/09/2010
Application #:
12612743
Filing Dt:
11/05/2009
Publication #:
US20100047990
Pub Dt:
02/25/2010
Title:
METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR
68
Patent #:
7989312
Issue Dt:
08/02/2011
Application #:
12612957
Filing Dt:
11/05/2009
Publication #:
US20100044759
Pub Dt:
02/25/2010
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
69
Patent #:
8298948
Issue Dt:
10/30/2012
Application #:
12613551
Filing Dt:
11/06/2009
Publication #:
US20110108990
Pub Dt:
05/12/2011
Title:
CAPPING OF COPPER INTERCONNECT LINES IN INTEGRATED CIRCUIT DEVICES
70
Patent #:
8587063
Issue Dt:
11/19/2013
Application #:
12613574
Filing Dt:
11/06/2009
Publication #:
US20110108943
Pub Dt:
05/12/2011
Title:
HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS
71
Patent #:
8323868
Issue Dt:
12/04/2012
Application #:
12613800
Filing Dt:
11/06/2009
Publication #:
US20110111339
Pub Dt:
05/12/2011
Title:
BILAYER SYSTEMS INCLUDING A POLYDIMETHYLGLUTARIMIDE-BASED BOTTOM LAYER AND COMPOSITIONS THEREOF
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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