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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
06/11/2013
Application #:
12892465
Filing Dt:
09/28/2010
Publication #:
Pub Dt:
03/29/2012
Title:
USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
2
Patent #:
Issue Dt:
02/28/2012
Application #:
12892950
Filing Dt:
09/29/2010
Title:
STRAINED THIN BODY SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DEVICE
3
Patent #:
Issue Dt:
11/01/2011
Application #:
12893051
Filing Dt:
09/29/2010
Publication #:
Pub Dt:
03/31/2011
Title:
SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY CORNER ROUNDING PRIOR TO COMPLETELY REMOVING A PLACEHOLDER MATERIAL
4
Patent #:
Issue Dt:
03/20/2012
Application #:
12893102
Filing Dt:
09/29/2010
Publication #:
Pub Dt:
03/31/2011
Title:
SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY PERFORMING A POLISHING PROCESS BASED ON A SACRIFICIAL FILL MATERIAL
5
Patent #:
Issue Dt:
08/13/2013
Application #:
12893329
Filing Dt:
09/29/2010
Publication #:
Pub Dt:
03/31/2011
Title:
OPTICAL SIGNAL TRANSFER IN A SEMICONDUCTOR DEVICE BY USING MONOLITHIC OPTO-ELECTRONIC COMPONENTS
6
Patent #:
Issue Dt:
12/25/2012
Application #:
12893808
Filing Dt:
09/29/2010
Publication #:
Pub Dt:
05/05/2011
Title:
STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE
7
Patent #:
Issue Dt:
09/18/2012
Application #:
12894231
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
04/05/2012
Title:
CREATION OF LEAD-FREE SOLDER JOINT WITH INTERMETALLICS
8
Patent #:
Issue Dt:
07/01/2014
Application #:
12894286
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
04/05/2012
Title:
SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS
9
Patent #:
Issue Dt:
12/17/2013
Application #:
12894469
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
05/05/2011
Title:
METHOD FOR MAKING SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES WITH AN ENHANCED DIFFUSION BARRIER
10
Patent #:
Issue Dt:
07/17/2012
Application #:
12894484
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
01/27/2011
Title:
INCREASING RELIABILITY OF COPPER-BASED METALLIZATION STRUCTURES IN A MICROSTRUCTURE DEVICE BY USING ALUMINUM NITRIDE
11
Patent #:
Issue Dt:
05/17/2011
Application #:
12894579
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
05/05/2011
Title:
TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SACRIFICIAL CARBON SPACER
12
Patent #:
Issue Dt:
07/12/2011
Application #:
12894648
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
05/05/2011
Title:
FABRICATING VIAS OF DIFFERENT SIZE OF A SEMICONDUCTOR DEVICE BY SPLITTING THE VIA PATTERNING PROCESS
13
Patent #:
Issue Dt:
05/31/2011
Application #:
12894985
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
05/05/2011
Title:
CORNER ROUNDING IN A REPLACEMENT GATE APPROACH BASED ON A SACRIFICIAL FILL MATERIAL APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION
14
Patent #:
Issue Dt:
12/10/2013
Application #:
12895043
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
04/05/2012
Title:
CROSSBAR ARRAY MEMORY ELEMENTS AND RELATED READ METHODS
15
Patent #:
Issue Dt:
02/05/2013
Application #:
12895116
Filing Dt:
09/30/2010
Publication #:
Pub Dt:
05/05/2011
Title:
METHOD FOR FORMING SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES
16
Patent #:
Issue Dt:
12/25/2012
Application #:
12897021
Filing Dt:
10/04/2010
Publication #:
Pub Dt:
04/05/2012
Title:
SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE
17
Patent #:
Issue Dt:
08/13/2013
Application #:
12897230
Filing Dt:
10/04/2010
Publication #:
Pub Dt:
04/05/2012
Title:
ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
18
Patent #:
Issue Dt:
09/16/2014
Application #:
12897295
Filing Dt:
10/04/2010
Publication #:
Pub Dt:
04/05/2012
Title:
PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE
19
Patent #:
Issue Dt:
06/04/2013
Application #:
12897964
Filing Dt:
10/05/2010
Publication #:
Pub Dt:
10/20/2011
Title:
PHASED ARRAY MILLIMETER WAVE IMAGING TECHNIQUES
20
Patent #:
Issue Dt:
04/02/2013
Application #:
12897983
Filing Dt:
10/05/2010
Publication #:
Pub Dt:
04/05/2012
Title:
STRUCTURE, DESIGN STRUCTURE AND PROCESS FOR INCREASING MAGNITUDE OF DEVICE THRESHOLD VOLTAGE FOR LOW POWER APPLICATIONS
21
Patent #:
Issue Dt:
04/09/2013
Application #:
12898822
Filing Dt:
10/06/2010
Publication #:
Pub Dt:
05/05/2011
Title:
ENHANCED ADHESION OF PECVD CARBON ON DIELECTRIC MATERIALS BY PROVIDING AN ADHESION INTERFACE
22
Patent #:
Issue Dt:
06/18/2013
Application #:
12898924
Filing Dt:
10/06/2010
Publication #:
Pub Dt:
04/12/2012
Title:
DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP
23
Patent #:
Issue Dt:
08/21/2012
Application #:
12898958
Filing Dt:
10/06/2010
Publication #:
Pub Dt:
05/05/2011
Title:
STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON GLOBALLY STRAINED SEMICONDUCTOR BASE LAYERS
24
Patent #:
Issue Dt:
03/27/2012
Application #:
12899333
Filing Dt:
10/06/2010
Publication #:
Pub Dt:
06/02/2011
Title:
TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED ON THE BASIS OF A SIMPLIFIED SPACER REGIME
25
Patent #:
Issue Dt:
08/07/2012
Application #:
12899638
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
04/12/2012
Title:
TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE
26
Patent #:
Issue Dt:
11/27/2012
Application #:
12899676
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
06/02/2011
Title:
PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY AN EARLY EXTENSION IMPLANTATION
27
Patent #:
Issue Dt:
05/26/2015
Application #:
12899691
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
04/12/2012
Title:
ENGINEERING MULTIPLE THRESHOLD VOLTAGES IN AN INTEGRATED CIRCUIT
28
Patent #:
Issue Dt:
04/02/2013
Application #:
12899868
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
02/03/2011
Title:
SELF HEATING MONITOR FOR SIGE AND SOI CMOS DEVICES
29
Patent #:
Issue Dt:
08/09/2011
Application #:
12899979
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
02/03/2011
Title:
SHARED RESOURCES IN A CHIP MULTIPROCESSOR
30
Patent #:
Issue Dt:
04/02/2013
Application #:
12900085
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
04/12/2012
Title:
METHOD AND APPARATUS FOR ROUTING DISPATCHING AND ROUTING RETICLES
31
Patent #:
Issue Dt:
07/24/2012
Application #:
12900095
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
04/12/2012
Title:
METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR
32
Patent #:
Issue Dt:
09/04/2012
Application #:
12900578
Filing Dt:
10/08/2010
Publication #:
Pub Dt:
06/02/2011
Title:
PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY REDUCING A WIDTH OF OFFSET SPACERS
33
Patent #:
Issue Dt:
08/05/2014
Application #:
12901079
Filing Dt:
10/08/2010
Publication #:
Pub Dt:
01/27/2011
Title:
HEATER AND MEMORY CELL, MEMORY DEVICE AND RECORDING HEAD INCLUDING THE HEATER
34
Patent #:
Issue Dt:
06/14/2011
Application #:
12901148
Filing Dt:
10/08/2010
Publication #:
Pub Dt:
01/27/2011
Title:
LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES
35
Patent #:
Issue Dt:
04/14/2015
Application #:
12901733
Filing Dt:
10/11/2010
Publication #:
Pub Dt:
04/12/2012
Title:
SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE
36
Patent #:
Issue Dt:
01/08/2013
Application #:
12902343
Filing Dt:
10/12/2010
Publication #:
Pub Dt:
04/12/2012
Title:
IMPLEMENTING ROUTING FIRST FOR RAPID PROTOTYPING AND IMPROVED WIRING OF HETEROGENEOUS HIERARCHICAL INTEGRATED CIRCUITS
37
Patent #:
Issue Dt:
09/17/2013
Application #:
12902624
Filing Dt:
10/12/2010
Publication #:
Pub Dt:
04/12/2012
Title:
STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE
38
Patent #:
Issue Dt:
03/26/2013
Application #:
12902776
Filing Dt:
10/12/2010
Publication #:
Pub Dt:
04/12/2012
Title:
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
39
Patent #:
Issue Dt:
10/30/2012
Application #:
12902793
Filing Dt:
10/12/2010
Publication #:
Pub Dt:
04/12/2012
Title:
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
40
Patent #:
Issue Dt:
10/18/2011
Application #:
12902944
Filing Dt:
10/12/2010
Publication #:
Pub Dt:
02/03/2011
Title:
SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT
41
Patent #:
Issue Dt:
07/01/2014
Application #:
12903695
Filing Dt:
10/13/2010
Publication #:
Pub Dt:
04/19/2012
Title:
MULTI-WRITE ENDURANCE AND ERROR CONTROL CODING OF NON-VOLATILE MEMORIES
42
Patent #:
Issue Dt:
08/09/2011
Application #:
12904346
Filing Dt:
10/14/2010
Title:
SURFACE CLEANING USING SACRIFICIAL GETTER LAYER
43
Patent #:
Issue Dt:
07/23/2013
Application #:
12904348
Filing Dt:
10/14/2010
Publication #:
Pub Dt:
04/19/2012
Title:
METHOD FOR SIMULTANEOUSLY FORMING A THROUGH SILICON VIA AND A DEEP TRENCH STRUCTURE
44
Patent #:
Issue Dt:
09/10/2013
Application #:
12904435
Filing Dt:
10/14/2010
Publication #:
Pub Dt:
04/19/2012
Title:
VERTICAL SILICIDE E-FUSE
45
Patent #:
Issue Dt:
07/23/2013
Application #:
12904597
Filing Dt:
10/14/2010
Publication #:
Pub Dt:
04/19/2012
Title:
METHOD TO ELECTRODEPOSIT NICKEL ON SILICON FOR FORMING CONTROLLABLE NICKEL SILICIDE
46
Patent #:
Issue Dt:
02/25/2014
Application #:
12905158
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
04/19/2012
Title:
Method and Structure for pFET Junction Profile With SiGe Channel
47
Patent #:
Issue Dt:
03/26/2013
Application #:
12905383
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
06/02/2011
Title:
PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT
48
Patent #:
Issue Dt:
07/31/2012
Application #:
12905440
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
06/02/2011
Title:
HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING
49
Patent #:
Issue Dt:
01/22/2013
Application #:
12905501
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
06/02/2011
Title:
WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE
50
Patent #:
Issue Dt:
01/15/2013
Application #:
12905575
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
04/19/2012
Title:
INTEGRATED PLANAR AND MULTIPLE GATE FETS
51
Patent #:
Issue Dt:
08/21/2012
Application #:
12905619
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
06/02/2011
Title:
ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS
52
Patent #:
Issue Dt:
12/11/2012
Application #:
12905655
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
06/02/2011
Title:
CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL
53
Patent #:
Issue Dt:
09/17/2013
Application #:
12905711
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
06/30/2011
Title:
PREDOPED SEMICONDUCTOR MATERIAL FOR A HIGH-K METAL GATE ELECTRODE STRUCTURE OF P- AND N-CHANNEL TRANSISTORS
54
Patent #:
Issue Dt:
06/12/2012
Application #:
12905805
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
04/19/2012
Title:
SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGIONS AND DEFECT-FREE ACTIVE SEMICONDUCTOR MATERIAL
55
Patent #:
Issue Dt:
08/14/2012
Application #:
12906690
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
02/10/2011
Title:
NEGATIVE THERMAL EXPANSION SYSTEM (NTES) DEVICE FOR TCE COMPENSATION IN ELASTOMER COMPOSITES AND CONDUCTIVE ELASTOMER INTERCONNECTS IN MICROELECTRONIC PACKAGING
56
Patent #:
Issue Dt:
07/01/2014
Application #:
12906697
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
04/19/2012
Title:
EMBEDDED VERTICAL OPTICAL GRATING FOR HETEROGENEOUS INTEGRATION
57
Patent #:
Issue Dt:
01/28/2014
Application #:
12906707
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
04/19/2012
Title:
METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE
58
Patent #:
Issue Dt:
01/08/2013
Application #:
12907105
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
04/19/2012
Title:
LOW TRIGGER VOLTAGE ELECTROSTATIC DISCHARGE NFET IN TRIPLE WELL CMOS TECHNOLOGY
59
Patent #:
Issue Dt:
12/02/2014
Application #:
12907186
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
02/10/2011
Title:
SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE
60
Patent #:
Issue Dt:
06/10/2014
Application #:
12907596
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
06/30/2011
Title:
ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE
61
Patent #:
Issue Dt:
10/18/2011
Application #:
12907675
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
06/30/2011
Title:
ENHANCED INTEGRITY OF A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL SPACER FOR CAP REMOVAL
62
Patent #:
Issue Dt:
02/25/2014
Application #:
12907731
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
06/30/2011
Title:
SEMICONDUCTOR RESISTORS FORMED AT A LOWER HEIGHT LEVEL IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES
63
Patent #:
Issue Dt:
01/28/2014
Application #:
12907904
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
04/19/2012
Title:
PREVENTION AND REMEDIATION OF DAMAGE TO OPTICAL SURFACES
64
Patent #:
Issue Dt:
12/27/2011
Application #:
12908016
Filing Dt:
10/20/2010
Title:
REPLACEMENT METAL GATE METHOD
65
Patent #:
Issue Dt:
02/04/2014
Application #:
12908024
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
04/26/2012
Title:
STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR
66
Patent #:
Issue Dt:
05/13/2014
Application #:
12908053
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
06/30/2011
Title:
ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A RECESS PRIOR TO THE WELL IMPLANTATION
67
Patent #:
Issue Dt:
06/11/2013
Application #:
12908306
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
04/26/2012
Title:
LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS
68
Patent #:
Issue Dt:
03/25/2014
Application #:
12908554
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
02/10/2011
Title:
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
69
Patent #:
Issue Dt:
01/08/2013
Application #:
12909149
Filing Dt:
10/21/2010
Publication #:
Pub Dt:
06/30/2011
Title:
ENHANCED CONFINEMENT OF HIGH-K METAL GATE ELECTRODE STRUCTURES BY REDUCING MATERIAL EROSION OF A DIELECTRIC CAP LAYER UPON FORMING A STRAIN-INDUCING SEMICONDUCTOR ALLOY
70
Patent #:
Issue Dt:
03/11/2014
Application #:
12909291
Filing Dt:
10/21/2010
Publication #:
Pub Dt:
06/30/2011
Title:
HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED AT DIFFERENT PROCESS STAGES OF A SEMICONDUCTOR DEVICE
71
Patent #:
Issue Dt:
07/03/2012
Application #:
12909325
Filing Dt:
10/21/2010
Publication #:
Pub Dt:
04/26/2012
Title:
SEMICONDUCTOR STRUCTURE AND METHODS OF MANUFACTURE
72
Patent #:
Issue Dt:
02/17/2015
Application #:
12910075
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES
73
Patent #:
Issue Dt:
10/09/2012
Application #:
12910144
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
REDUCING ENERGY CONSUMPTION AND OPTIMIZING WORKLOAD AND PERFORMANCE IN MULTI-TIER STORAGE SYSTEMS USING EXTENT-LEVEL DYNAMIC TIERING
74
Patent #:
Issue Dt:
12/04/2012
Application #:
12910236
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
02/17/2011
Title:
MAGNETIC MATERIALS HAVING SUPERPARAMAGNETIC PARTICLES
75
Patent #:
Issue Dt:
07/23/2013
Application #:
12910336
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
05/12/2011
Title:
PROVIDING SECONDARY POWER PINS IN INTEGRATED CIRCUIT DESIGN
76
Patent #:
Issue Dt:
03/05/2013
Application #:
12910979
Filing Dt:
10/25/2010
Publication #:
Pub Dt:
06/30/2011
Title:
CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES FORMED ON THE BASIS OF A PARTIALLY APPLIED ACTIVATION LAYER
77
Patent #:
Issue Dt:
11/25/2014
Application #:
12911327
Filing Dt:
10/25/2010
Publication #:
Pub Dt:
04/26/2012
Title:
ON-CHIP TUNABLE TRANSMISSION LINES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
78
Patent #:
Issue Dt:
05/22/2012
Application #:
12911379
Filing Dt:
10/25/2010
Publication #:
Pub Dt:
02/10/2011
Title:
PROGRAMMABLE SEMICONDUCTOR DEVICE
79
Patent #:
Issue Dt:
05/14/2013
Application #:
12911833
Filing Dt:
10/26/2010
Publication #:
Pub Dt:
04/26/2012
Title:
FABRICATING KESTERITE SOLAR CELLS AND PARTS THEREOF
80
Patent #:
Issue Dt:
01/15/2013
Application #:
12912819
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION
81
Patent #:
Issue Dt:
04/01/2014
Application #:
12912897
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SEMICONDUCTOR DEVICE HAVING LOCALIZED EXTREMELY THIN SILICON ON INSULATOR CHANNEL REGION
82
Patent #:
Issue Dt:
10/30/2012
Application #:
12912940
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
83
Patent #:
Issue Dt:
11/26/2013
Application #:
12912963
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
84
Patent #:
Issue Dt:
07/09/2013
Application #:
12914123
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
08/04/2011
Title:
SEMICONDUCTOR ELEMENT COMPRISING A LOW VARIATION SUBSTRATE DIODE
85
Patent #:
Issue Dt:
03/05/2013
Application #:
12914132
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SEALED AIR GAP FOR SEMICONDUCTOR CHIP
86
Patent #:
Issue Dt:
02/26/2013
Application #:
12914234
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
08/04/2011
Title:
SEMICONDUCTOR DEVICE FORMED BY A REPLACEMENT GATE APPROACH BASED ON AN EARLY WORK FUNCTION METAL
87
Patent #:
Issue Dt:
02/04/2014
Application #:
12914367
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
02/17/2011
Title:
METHOD FOR QUANTIFYING THE MANUFACTURING COMPLEXITY OF ELECTRICAL DESIGNS
88
Patent #:
Issue Dt:
04/02/2013
Application #:
12914570
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
08/04/2011
Title:
REPLACEMENT GATE APPROACH BASED ON A REVERSE OFFSET SPACER APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION
89
Patent #:
Issue Dt:
01/15/2013
Application #:
12914573
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES
90
Patent #:
Issue Dt:
08/28/2012
Application #:
12914644
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
OPTIMIZED SEMICONDUCTOR PACKAGING IN A THREE-DIMENSIONAL STACK
91
Patent #:
Issue Dt:
11/01/2011
Application #:
12914663
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
08/04/2011
Title:
SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE WINDOW AREA
92
Patent #:
Issue Dt:
04/23/2013
Application #:
12914730
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
Thermal Power Plane for Integrated Circuits
93
Patent #:
Issue Dt:
05/07/2013
Application #:
12915168
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
08/04/2011
Title:
SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOGRAPHY TOLERANT CONTACT STRUCTURE
94
Patent #:
Issue Dt:
11/01/2011
Application #:
12915216
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
08/04/2011
Title:
REDUCING CONTAMINATION IN A PROCESS FLOW OF FORMING A CHANNEL SEMICONDUCTOR ALLOY IN A SEMICONDUCTOR DEVICE
95
Patent #:
Issue Dt:
07/31/2012
Application #:
12915463
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS
96
Patent #:
Issue Dt:
12/31/2013
Application #:
12915888
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
ANTI-BLOOMING PIXEL SENSOR CELL WITH ACTIVE NEUTRAL DENSITY FILTER, METHODS OF MANUFACTURE, AND DESIGN STRUCTURE
97
Patent #:
Issue Dt:
01/01/2013
Application #:
12915923
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SPLIT-LAYER DESIGN FOR DOUBLE PATTERNING LITHOGRAPHY
98
Patent #:
Issue Dt:
02/21/2012
Application #:
12916681
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
02/24/2011
Title:
REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT
99
Patent #:
Issue Dt:
07/31/2012
Application #:
12916864
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
05/03/2012
Title:
LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE
100
Patent #:
Issue Dt:
07/31/2012
Application #:
12917029
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
05/03/2012
Title:
STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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