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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
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Patent #:	8946013	Issue Dt:	02/03/2015	Application #:	13364663	Filing Dt:	02/02/2012
Publication #:	US20120126319	Pub Dt:	05/24/2012
Title:	LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE

Patent #:	9177826	Issue Dt:	11/03/2015	Application #:	13364671	Filing Dt:	02/02/2012
Publication #:	US20130203266	Pub Dt:	08/08/2013
Title:	METHODS OF FORMING METAL NITRIDE MATERIALS

Patent #:	8889504	Issue Dt:	11/18/2014	Application #:	13364753	Filing Dt:	02/02/2012
Publication #:	US20120135591	Pub Dt:	05/31/2012
Title:	SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING

Patent #:	8743586	Issue Dt:	06/03/2014	Application #:	13364759	Filing Dt:	02/02/2012
Publication #:	US20130033918	Pub Dt:	02/07/2013
Title:	METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER

Patent #:	8507375	Issue Dt:	08/13/2013	Application #:	13364976	Filing Dt:	02/02/2012
Publication #:	US20130200471	Pub Dt:	08/08/2013
Title:	ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD

Patent #:	8580628	Issue Dt:	11/12/2013	Application #:	13365030	Filing Dt:	02/02/2012
Publication #:	US20130200441	Pub Dt:	08/08/2013
Title:	INTEGRATED CIRCUIT CONTACT STRUCTURE AND METHOD

Patent #:	8421220	Issue Dt:	04/16/2013	Application #:	13365505	Filing Dt:	02/03/2012
Publication #:	US20120133051	Pub Dt:	05/31/2012
Title:	SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE

Patent #:	8618581	Issue Dt:	12/31/2013	Application #:	13365577	Filing Dt:	02/03/2012
Publication #:	US20120132886	Pub Dt:	05/31/2012
Title:	NANOFLUIDIC FIELD EFFECT TRANSISTOR BASED ON SURFACE CHARGE MODULATED NANOCHANNEL

Patent #:	8399933	Issue Dt:	03/19/2013	Application #:	13365764	Filing Dt:	02/03/2012
Publication #:	US20120199941	Pub Dt:	08/09/2012
Title:	SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)

Patent #:	8612911	Issue Dt:	12/17/2013	Application #:	13365961	Filing Dt:	02/03/2012
Publication #:	US20120216160	Pub Dt:	08/23/2012
Title:	ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT

Patent #:	8627263	Issue Dt:	01/07/2014	Application #:	13365989	Filing Dt:	02/03/2012
Publication #:	US20120216168	Pub Dt:	08/23/2012
Title:	GATE CONFIGURATION DETERMINATION AND SELECTION FROM STANDARD CELL LIBRARY

Patent #:	8437201	Issue Dt:	05/07/2013	Application #:	13366804	Filing Dt:	02/06/2012
Publication #:	US20120134221	Pub Dt:	05/31/2012
Title:	WORD-LINE LEVEL SHIFT CIRCUIT

Patent #:	8399927	Issue Dt:	03/19/2013	Application #:	13367646	Filing Dt:	02/07/2012
Publication #:	US20120132992	Pub Dt:	05/31/2012
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE

Patent #:	8900964	Issue Dt:	12/02/2014	Application #:	13367895	Filing Dt:	02/07/2012
Publication #:	US20130200521	Pub Dt:	08/08/2013
Title:	INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL

Patent #:	9105571	Issue Dt:	08/11/2015	Application #:	13368750	Filing Dt:	02/08/2012
Publication #:	US20130200443	Pub Dt:	08/08/2013
Title:	Interface Engineering to Optimize Metal-III-V Contacts

Patent #:	8637374	Issue Dt:	01/28/2014	Application #:	13368901	Filing Dt:	02/08/2012
Publication #:	US20120142158	Pub Dt:	06/07/2012
Title:	Method of Fabricating Self-Aligned Nanotube Field Effect Transistor

Patent #:	8659937	Issue Dt:	02/25/2014	Application #:	13368918	Filing Dt:	02/08/2012
Publication #:	US20130201753	Pub Dt:	08/08/2013
Title:	IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM

Patent #:	8614117	Issue Dt:	12/24/2013	Application #:	13369246	Filing Dt:	02/08/2012
Publication #:	US20130200330	Pub Dt:	08/08/2013
Title:	SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR

Patent #:	8927380	Issue Dt:	01/06/2015	Application #:	13369261	Filing Dt:	02/08/2012
Publication #:	US20130200942	Pub Dt:	08/08/2013
Title:	SOI BIPOLAR JUNCTION TRANSISTOR WITH SUBSTRATE BIAS VOLTAGES

Patent #:	8338949	Issue Dt:	12/25/2012	Application #:	13369273	Filing Dt:	02/08/2012
Publication #:	US20120138349	Pub Dt:	06/07/2012
Title:	SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS

Patent #:	9059248	Issue Dt:	06/16/2015	Application #:	13369382	Filing Dt:	02/09/2012
Publication #:	US20130207188	Pub Dt:	08/15/2013
Title:	JUNCTION BUTTING ON SOI BY RAISED EPITAXIAL STRUCTURE AND METHOD

Patent #:	8354320	Issue Dt:	01/15/2013	Application #:	13369482	Filing Dt:	02/09/2012
Title:	METHODS OF CONTROLLING FIN HEIGHT OF FINFET DEVICES BY PERFORMING A DIRECTIONAL DEPOSITION PROCESS

Patent #:	8273648	Issue Dt:	09/25/2012	Application #:	13369592	Filing Dt:	02/09/2012
Publication #:	US20120135599	Pub Dt:	05/31/2012
Title:	CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE

Patent #:	9059394	Issue Dt:	06/16/2015	Application #:	13369655	Filing Dt:	02/09/2012
Publication #:	US20120139119	Pub Dt:	06/07/2012
Title:	SELF-ALIGNED LOWER BOTTOM ELECTRODE

Patent #:	9548378	Issue Dt:	01/17/2017	Application #:	13369856	Filing Dt:	02/09/2012
Publication #:	US20130210216	Pub Dt:	08/15/2013
Title:	EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES

Patent #:	8736277	Issue Dt:	05/27/2014	Application #:	13369872	Filing Dt:	02/09/2012
Publication #:	US20130207765	Pub Dt:	08/15/2013
Title:	INTEGRATED TRANSFORMERS

Patent #:	8589844	Issue Dt:	11/19/2013	Application #:	13369938	Filing Dt:	02/09/2012
Publication #:	US20130212548	Pub Dt:	08/15/2013
Title:	METHODS FOR ANALYZING DESIGN RULES

Patent #:	8410816	Issue Dt:	04/02/2013	Application #:	13370144	Filing Dt:	02/09/2012
Title:	LOW-SWING SIGNALING SCHEME FOR DATA COMMUNICATION

Patent #:	8476137	Issue Dt:	07/02/2013	Application #:	13370722	Filing Dt:	02/10/2012
Title:	Methods of FinFET Height Control

Patent #:	8629501	Issue Dt:	01/14/2014	Application #:	13370898	Filing Dt:	02/10/2012
Publication #:	US20120139081	Pub Dt:	06/07/2012
Title:	STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES

Patent #:	8835209	Issue Dt:	09/16/2014	Application #:	13370944	Filing Dt:	02/10/2012
Publication #:	US20120211838	Pub Dt:	08/23/2012
Title:	COMPLEMENTARY TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EPITAXIALLY FORMED SEMICONDUCTOR MATERIALS IN THE DRAIN AND SOURCE AREAS

Patent #:	8722523	Issue Dt:	05/13/2014	Application #:	13371049	Filing Dt:	02/10/2012
Publication #:	US20120211844	Pub Dt:	08/23/2012
Title:	SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE

Patent #:	8561880	Issue Dt:	10/22/2013	Application #:	13371430	Filing Dt:	02/11/2012
Publication #:	US20130206351	Pub Dt:	08/15/2013
Title:	FORMING METAL PREFORMS AND METAL BALLS

Patent #:	8569168	Issue Dt:	10/29/2013	Application #:	13371493	Filing Dt:	02/13/2012
Publication #:	US20130207270	Pub Dt:	08/15/2013
Title:	DUAL-METAL SELF-ALIGNED WIRES AND VIAS

Patent #:	8932961	Issue Dt:	01/13/2015	Application #:	13371585	Filing Dt:	02/13/2012
Publication #:	US20130207108	Pub Dt:	08/15/2013
Title:	Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques

Patent #:	8932931	Issue Dt:	01/13/2015	Application #:	13371605	Filing Dt:	02/13/2012
Publication #:	US20130207235	Pub Dt:	08/15/2013
Title:	SELF-ALIGNED EMITTER-BASE REGION

Patent #:	8328156	Issue Dt:	12/11/2012	Application #:	13371840	Filing Dt:	02/13/2012
Publication #:	US20120138769	Pub Dt:	06/07/2012
Title:	TECHNIQUES FOR FORMING SOLDER BUMP INTERCONNECTS

Patent #:	8697561	Issue Dt:	04/15/2014	Application #:	13372058	Filing Dt:	02/13/2012
Publication #:	US20120142182	Pub Dt:	06/07/2012
Title:	MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION

Patent #:	8817570	Issue Dt:	08/26/2014	Application #:	13372085	Filing Dt:	02/13/2012
Publication #:	US20130208555	Pub Dt:	08/15/2013
Title:	DEVICES HAVING BIAS TEMPERATURE INSTABILITY COMPENSATION

Patent #:	8698082	Issue Dt:	04/15/2014	Application #:	13372466	Filing Dt:	02/13/2012
Publication #:	US20130075610	Pub Dt:	03/28/2013
Title:	HIGH-FIDELITY DEVICE FOR SINGLE-SHOT PULSE CONTRAST MEASUREMENT BASED ON QUASI-PHASE-MATCHING (QPM)

Patent #:	8835245	Issue Dt:	09/16/2014	Application #:	13372604	Filing Dt:	02/14/2012
Publication #:	US20120211837	Pub Dt:	08/23/2012
Title:	SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS

Patent #:	8507892	Issue Dt:	08/13/2013	Application #:	13372714	Filing Dt:	02/14/2012
Publication #:	US20120138900	Pub Dt:	06/07/2012
Title:	OMEGA SHAPED NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS

Patent #:	8680589	Issue Dt:	03/25/2014	Application #:	13372719	Filing Dt:	02/14/2012
Publication #:	US20120146000	Pub Dt:	06/14/2012
Title:	OMEGA SHAPED NANOWIRE FIELD EFFECT TRANSISTORS

Patent #:	8652889	Issue Dt:	02/18/2014	Application #:	13372837	Filing Dt:	02/14/2012
Publication #:	US20120211808	Pub Dt:	08/23/2012
Title:	FIN-TRANSISTOR FORMED ON A PATTERNED STI REGION BY LATE FIN ETCH

Patent #:	9018102	Issue Dt:	04/28/2015	Application #:	13372901	Filing Dt:	02/14/2012
Publication #:	US20120214305	Pub Dt:	08/23/2012
Title:	Technique for Reducing Plasma-Induced Etch Damage During the Formation of Vias in Interlayer Dielectrics by Modified RF Power Ramp-Up

Patent #:	9496140	Issue Dt:	11/15/2016	Application #:	13372974	Filing Dt:	02/14/2012
Publication #:	US20120138132	Pub Dt:	06/07/2012
Title:	SILICON WAFER BASED STRUCTURE FOR HETEROSTRUCTURE SOLAR CELLS

Patent #:	8536632	Issue Dt:	09/17/2013	Application #:	13396291	Filing Dt:	02/14/2012
Publication #:	US20120146112	Pub Dt:	06/14/2012
Title:	FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY

Patent #:	8519497	Issue Dt:	08/27/2013	Application #:	13396998	Filing Dt:	02/15/2012
Publication #:	US20120141748	Pub Dt:	06/07/2012
Title:	Template-Registered DiBlock Copolymer Mask for MRAM Device Formation

Patent #:	8288270	Issue Dt:	10/16/2012	Application #:	13397004	Filing Dt:	02/15/2012
Publication #:	US20120199983	Pub Dt:	08/09/2012
Title:	ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN

Patent #:	8673696	Issue Dt:	03/18/2014	Application #:	13397345	Filing Dt:	02/15/2012
Publication #:	US20120217582	Pub Dt:	08/30/2012
Title:	SOI Semiconductor Device Comprising a Substrate Diode with Reduced Metal Silicide Leakage

Patent #:	8669182	Issue Dt:	03/11/2014	Application #:	13398070	Filing Dt:	02/16/2012
Publication #:	US20120149191	Pub Dt:	06/14/2012
Title:	METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS

Patent #:	9105577	Issue Dt:	08/11/2015	Application #:	13398151	Filing Dt:	02/16/2012
Publication #:	US20130214356	Pub Dt:	08/22/2013
Title:	MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE

Patent #:	8798484	Issue Dt:	08/05/2014	Application #:	13398190	Filing Dt:	02/16/2012
Publication #:	US20130216241	Pub Dt:	08/22/2013
Title:	OPTICAL RECEIVER USING INFINITE IMPULSE RESPONSE DECISION FEEDBACK EQUALIZATION

Patent #:	8637371	Issue Dt:	01/28/2014	Application #:	13398339	Filing Dt:	02/16/2012
Publication #:	US20130214357	Pub Dt:	08/22/2013
Title:	NON-PLANAR MOSFET STRUCTURES WITH ASYMMETRIC RECESSED SOURCE DRAINS AND METHODS FOR MAKING THE SAME

Patent #:	8829572	Issue Dt:	09/09/2014	Application #:	13398408	Filing Dt:	02/16/2012
Publication #:	US20120146104	Pub Dt:	06/14/2012
Title:	STRUCTURE AND LAYOUT OF A FET PRIME CELL

Patent #:	8738167	Issue Dt:	05/27/2014	Application #:	13398481	Filing Dt:	02/16/2012
Publication #:	US20120149173	Pub Dt:	06/14/2012
Title:	3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL

Patent #:	8375345	Issue Dt:	02/12/2013	Application #:	13398490	Filing Dt:	02/16/2012
Title:	SOFT-BOUNDED HIERARCHICAL SYNTHESIS

Patent #:	8629553	Issue Dt:	01/14/2014	Application #:	13398505	Filing Dt:	02/16/2012
Publication #:	US20120153429	Pub Dt:	06/21/2012
Title:	3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL

Patent #:	8552414	Issue Dt:	10/08/2013	Application #:	13398518	Filing Dt:	02/16/2012
Publication #:	US20120140571	Pub Dt:	06/07/2012
Title:	ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE

Patent #:	9059250	Issue Dt:	06/16/2015	Application #:	13398875	Filing Dt:	02/17/2012
Publication #:	US20130214391	Pub Dt:	08/22/2013
Title:	Lateral-Dimension-Reducing Metallic Hard Mask Etch

Patent #:	8673759	Issue Dt:	03/18/2014	Application #:	13398991	Filing Dt:	02/17/2012
Publication #:	US20130217221	Pub Dt:	08/22/2013
Title:	DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES

Patent #:	8704583	Issue Dt:	04/22/2014	Application #:	13399054	Filing Dt:	02/17/2012
Publication #:	US20130214865	Pub Dt:	08/22/2013
Title:	CAPACITIVE LEVEL-SHIFTING CIRCUITS AND METHODS FOR ADDING DC OFFSETS TO OUTPUT OF CURRENT-INTEGRATING AMPLIFIER

Patent #:	8962467	Issue Dt:	02/24/2015	Application #:	13399266	Filing Dt:	02/17/2012
Publication #:	US20130214894	Pub Dt:	08/22/2013
Title:	METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY

Patent #:	8323608	Issue Dt:	12/04/2012	Application #:	13399612	Filing Dt:	02/17/2012
Publication #:	US20120148474	Pub Dt:	06/14/2012
Title:	EMBEDDED NANOPARTICLE FILMS AND METHOD FOR THEIR FORMATION IN SELECTIVE AREAS ON A SURFACE

Patent #:	8541286	Issue Dt:	09/24/2013	Application #:	13399674	Filing Dt:	02/17/2012
Publication #:	US20130217204	Pub Dt:	08/22/2013
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS

Patent #:	8964825	Issue Dt:	02/24/2015	Application #:	13399675	Filing Dt:	02/17/2012
Publication #:	US20130215954	Pub Dt:	08/22/2013
Title:	ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION

Patent #:	8679940	Issue Dt:	03/25/2014	Application #:	13399727	Filing Dt:	02/17/2012
Publication #:	US20130217205	Pub Dt:	08/22/2013
Title:	METHODS FOR FABRICATING SEMICONDUCTOR DEVICES WITH ISOLATION REGIONS HAVING UNIFORM STEPHEIGHTS

Patent #:	8642419	Issue Dt:	02/04/2014	Application #:	13400407	Filing Dt:	02/20/2012
Publication #:	US20130214381	Pub Dt:	08/22/2013
Title:	METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES

Patent #:	8555215	Issue Dt:	10/08/2013	Application #:	13400445	Filing Dt:	02/20/2012
Publication #:	US20130219347	Pub Dt:	08/22/2013
Title:	METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS

Patent #:	8497202	Issue Dt:	07/30/2013	Application #:	13400610	Filing Dt:	02/21/2012
Publication #:	US20130214414	Pub Dt:	08/22/2013
Title:	INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES

Patent #:	8624395	Issue Dt:	01/07/2014	Application #:	13400900	Filing Dt:	02/21/2012
Publication #:	US20120161334	Pub Dt:	06/28/2012
Title:	REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE

Patent #:	8748302	Issue Dt:	06/10/2014	Application #:	13400981	Filing Dt:	02/21/2012
Publication #:	US20130214335	Pub Dt:	08/22/2013
Title:	REPLACEMENT GATE APPROACH FOR HIGH-K METAL GATE STACKS BY USING A MULTI-LAYER CONTACT LEVEL

Patent #:	8786051	Issue Dt:	07/22/2014	Application #:	13401064	Filing Dt:	02/21/2012
Publication #:	US20130214275	Pub Dt:	08/22/2013
Title:	TRANSISTOR HAVING A MONOCRYSTALLINE CENTER SECTION AND A POLYCRYSTALLINE OUTER SECTION, AND NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE

Patent #:	8773920	Issue Dt:	07/08/2014	Application #:	13401368	Filing Dt:	02/21/2012
Publication #:	US20130215686	Pub Dt:	08/22/2013
Title:	REFERENCE GENERATOR WITH PROGRAMMABLE M AND B PARAMETERS AND METHODS OF USE

Patent #:	8274072	Issue Dt:	09/25/2012	Application #:	13401967	Filing Dt:	02/22/2012
Publication #:	US20120146001	Pub Dt:	06/14/2012
Title:	ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET

Patent #:	8916337	Issue Dt:	12/23/2014	Application #:	13402068	Filing Dt:	02/22/2012
Publication #:	US20130216776	Pub Dt:	08/22/2013
Title:	DUAL HARD MASK LITHOGRAPHY PROCESS

Patent #:	8654594	Issue Dt:	02/18/2014	Application #:	13403252	Filing Dt:	02/23/2012
Publication #:	US20130223161	Pub Dt:	08/29/2013
Title:	VDIFF MAX LIMITER IN SRAMS FOR IMPROVED YIELD AND POWER

Patent #:	9231085	Issue Dt:	01/05/2016	Application #:	13403457	Filing Dt:	02/23/2012
Publication #:	US20120146145	Pub Dt:	06/14/2012
Title:	SEMICONDUCTOR STRUCTURE AND METHODS OF MANUFACTURE

Patent #:	8352894	Issue Dt:	01/08/2013	Application #:	13403799	Filing Dt:	02/23/2012
Publication #:	US20120216159	Pub Dt:	08/23/2012
Title:	VERIFICATION TECHNIQUES FOR LIVENESS CHECKING OF LOGIC DESIGNS

Patent #:	8681570	Issue Dt:	03/25/2014	Application #:	13404212	Filing Dt:	02/24/2012
Publication #:	US20130223162	Pub Dt:	08/29/2013
Title:	METHODS AND SYSTEMS FOR MEMORY DEVICES WITH ASYMMETRIC SWITCHING CHARACTERISTICS

Patent #:	9230725	Issue Dt:	01/05/2016	Application #:	13404485	Filing Dt:	02/24/2012
Publication #:	US20120151748	Pub Dt:	06/21/2012
Title:	METHODS OF DESIGNING AN INDUCTOR HAVING OPENING ENCLOSED WITHIN CONDUCTIVE LINE

Patent #:	9484457	Issue Dt:	11/01/2016	Application #:	13404759	Filing Dt:	02/24/2012
Publication #:	US20120217612	Pub Dt:	08/30/2012
Title:	VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES

Patent #:	8421228	Issue Dt:	04/16/2013	Application #:	13405443	Filing Dt:	02/27/2012
Publication #:	US20120153482	Pub Dt:	06/21/2012
Title:	STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES

Patent #:	8703386	Issue Dt:	04/22/2014	Application #:	13405587	Filing Dt:	02/27/2012
Publication #:	US20130224652	Pub Dt:	08/29/2013
Title:	METAL PEROXO COMPOUNDS WITH ORGANIC CO-LIGANDS FOR ELECTRON BEAM, DEEP UV AND EXTREME UV PHOTORESIST APPLICATIONS

Patent #:	8698128	Issue Dt:	04/15/2014	Application #:	13405682	Filing Dt:	02/27/2012
Publication #:	US20130221319	Pub Dt:	08/29/2013
Title:	GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FET'S ON BULK SEMICODUCTOR WAFERS

Patent #:	8674342	Issue Dt:	03/18/2014	Application #:	13405732	Filing Dt:	02/27/2012
Publication #:	US20130221328	Pub Dt:	08/29/2013
Title:	PAD-LESS GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETS ON BULK SEMICONDUCTOR WAFERS

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100

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Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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