|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13433401
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13433423
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
13433659
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13434495
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
TEST CASE PATTERN MATCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13434883
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
ENHANCED CAPACITANCE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13434934
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13434964
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13435056
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13435795
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13435828
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
SINGLE CYCLE DATA COPY FOR TWO-PORT SRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13436039
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13436045
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13436196
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13436323
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13437273
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
DISCONTINUOUS GUARD RING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13437309
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
STRESS REDUCTION MEANS FOR WARP CONTROL OF SUBSTRATES THROUGH CLAMPING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13437506
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
IDENTIFICATION OF LOCALIZABLE FUNCTION CALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13438230
|
Filing Dt:
|
04/03/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13438394
|
Filing Dt:
|
04/03/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
TECHNIQUES FOR USING MATERIAL SUBSTITUTION PROCESSES TO FORM REPLACEMENT METAL GATE ELECTRODES OF SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13438508
|
Filing Dt:
|
04/03/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13439016
|
Filing Dt:
|
04/04/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13439185
|
Filing Dt:
|
04/04/2012
|
Title:
|
METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES WITH DIFFERENT FIN HEIGHTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
13439188
|
Filing Dt:
|
04/04/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13439885
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
AUTOMATIC PARITY CHECKING IDENTIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13440514
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
SELF-PROTECTED DRAIN-EXTENDED METAL-OXIDE-SEMICONDUCTOR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13440546
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13441245
|
Filing Dt:
|
04/06/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13442062
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
Title:
|
STRUCTURE AND METHOD TO ENSURE CORRECT OPERATION OF AN INTEGRATED CIRCUIT IN THE PRESENCE OF IONIZING RADIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13442087
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13442090
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13442168
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13442322
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
METHOD OF FULL-FIELD SOLDER COVERAGE BY INVERTING A FILL HEAD AND A MOLD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13442683
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
PROCESSES FOR PREPARING STRESSED SEMICONDUCTOR WAFERS AND FOR PREPARING DEVICES INCLUDING THE STRESSED SEMICONDUCTOR WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
13443003
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
13443062
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
THERMALLY EXCITED NEAR-FIELD SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13443133
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13443418
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
Title:
|
BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13443426
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
VIA SELECTION IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13443427
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR SUB-PELLICLE DEFECT REDUCTION ON PHOTOMASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13444193
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13444343
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13444415
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
ADVANCED LOW K CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13444447
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13444647
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING THERMAL GATE, RELATED METHOD AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13445101
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
Nano/Microwire Solar Cell Fabricated by Nano/Microsphere Lithography
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13445128
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SOLVING CONGESTION USING NET GROUPING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13445172
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13445187
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
READ ONLY MEMORY (ROM) WITH REDUNDANCY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13445194
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13445428
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES SO AS TO TUNE THE THRESHOLD VOLTAGE OF SUCH DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13445475
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13445547
|
Filing Dt:
|
04/12/2012
|
Title:
|
METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13445596
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
METHODS OF RECESSING AN ACTIVE REGION AND STI STRUCTURES IN A COMMON ETCH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13445641
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13445719
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
INTEGRATED CIRCUITS HAVING IMPROVED METAL GATE STRUCTURES AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13446115
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
SWITCH WITH REDUCED INSERTION LOSS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13446350
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13446369
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
MITIGATION OF MASK DEFECTS BY PATTERN SHIFTING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13446418
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13446602
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13447019
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
FINFET STRUCTURES AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13447221
|
Filing Dt:
|
04/15/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
PROOF BASED BOUNDED MODEL CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13447751
|
Filing Dt:
|
04/16/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
REDUCING REPEATER POWER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13447982
|
Filing Dt:
|
04/16/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13448428
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Operation of a Noise Cancellation Device
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13448749
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13448775
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13449378
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13449419
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13449732
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13449741
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
Process of Multiple Exposures With Spin Castable Films
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13450004
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Design Structure for High Density Stable Static Random Access Memory
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13451054
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13451087
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13451382
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13451902
|
Filing Dt:
|
04/20/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13451947
|
Filing Dt:
|
04/20/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
13452857
|
Filing Dt:
|
04/21/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
NANOPORE CAPTURE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13453027
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
FLEXIBLE FIBER TO WAFER INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13453043
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METHOD FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13453165
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13453215
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
CMOS STRUCTURE INCLUDING NON-PLANAR HYBRID ORIENTATION SUBSTRATE WITH PLANAR GATE ELECTRODES & METHOD FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13453262
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13453426
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13453508
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13453740
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
SILICIDATION AND/OR GERMANIDATION ON SIGE OR GE BY COSPUTTERING NI AND GE AND USING AN INTRALAYER FOR THERMAL STABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13454220
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
Automated Fault and Recovery System
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13454433
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
INTEGRATED CIRCUITS HAVING PROTRUDING SOURCE AND DRAIN REGIONS AND METHODS FOR FORMING INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2015
|
Application #:
|
13454635
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13454709
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13454723
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13454928
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13454935
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
COMBINED SOFT DETECTION AND SOFT DECODING IN TAPE DRIVE STORAGE CHANNELS.
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13455174
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13455177
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13455394
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13455489
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
CET AND GATE CURRENT LEAKAGE REDUCTION IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY HEAT TREATMENT AFTER DIFFUSION LAYER REMOVAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13455507
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13455579
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13455616
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE FORMED USING REPLACEMENT GATE TECHNIQUES
|
|