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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
03/25/2014
Application #:
13455653
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE
2
Patent #:
Issue Dt:
05/07/2013
Application #:
13455725
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
3
Patent #:
Issue Dt:
06/24/2014
Application #:
13455732
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES
4
Patent #:
Issue Dt:
03/04/2014
Application #:
13456456
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/31/2013
Title:
NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT
5
Patent #:
Issue Dt:
09/02/2014
Application #:
13456596
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
12/27/2012
Title:
ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
6
Patent #:
Issue Dt:
12/23/2014
Application #:
13456745
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/25/2012
Title:
Generating Constraints in a Class Model
7
Patent #:
Issue Dt:
10/07/2014
Application #:
13457529
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
FINFET WITH ENHANCED EMBEDDED STRESSOR
8
Patent #:
Issue Dt:
02/03/2015
Application #:
13457601
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)
9
Patent #:
Issue Dt:
03/10/2015
Application #:
13457692
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE
10
Patent #:
Issue Dt:
08/09/2016
Application #:
13457722
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING
11
Patent #:
Issue Dt:
09/30/2014
Application #:
13457735
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
12
Patent #:
Issue Dt:
11/11/2014
Application #:
13457748
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS
13
Patent #:
Issue Dt:
06/14/2016
Application #:
13459460
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
10/31/2013
Title:
Assembly of Electronic and Optical Devices
14
Patent #:
Issue Dt:
06/24/2014
Application #:
13459785
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
10/31/2013
Title:
ELONGATED VIA STRUCTURES
15
Patent #:
Issue Dt:
02/18/2014
Application #:
13461912
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
STRUCTURE FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
16
Patent #:
Issue Dt:
08/12/2014
Application #:
13461935
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
DOPED CORE TRIGATE FET STRUCTURE AND METHOD
17
Patent #:
Issue Dt:
09/30/2014
Application #:
13461960
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
08/23/2012
Title:
PHOTORESIST COMPOSITIONS
18
Patent #:
Issue Dt:
12/02/2014
Application #:
13462185
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES
19
Patent #:
Issue Dt:
05/30/2017
Application #:
13462619
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
20
Patent #:
Issue Dt:
12/09/2014
Application #:
13462942
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
11/07/2013
Title:
INTEGRATED CIRCUIT WITH STRESS GENERATOR FOR STRESSING TEST DEVICES
21
Patent #:
Issue Dt:
04/12/2016
Application #:
13462964
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
08/30/2012
Title:
METHOD AND APPARATUS FOR PROBING A WAFER
22
Patent #:
Issue Dt:
05/20/2014
Application #:
13463283
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
23
Patent #:
Issue Dt:
04/08/2014
Application #:
13463592
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
11/07/2013
Title:
FINFET COMPATIBLE PC-BOUNDED ESD DIODE
24
Patent #:
Issue Dt:
07/02/2013
Application #:
13463879
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
08/30/2012
Title:
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
25
Patent #:
Issue Dt:
02/04/2014
Application #:
13464131
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
11/07/2013
Title:
CURRENT LEAKAGE IN RC ESD CLAMPS
26
Patent #:
Issue Dt:
09/16/2014
Application #:
13464267
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
10/03/2013
Title:
LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION
27
Patent #:
Issue Dt:
07/15/2014
Application #:
13464966
Filing Dt:
05/05/2012
Publication #:
Pub Dt:
11/07/2013
Title:
Techniques for the Fabrication of Thick Gate Dielectric
28
Patent #:
Issue Dt:
06/03/2014
Application #:
13465129
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
LAYOUT DESIGNS WITH VIA ROUTING STRUCTURES
29
Patent #:
Issue Dt:
03/25/2014
Application #:
13465134
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
30
Patent #:
Issue Dt:
05/26/2015
Application #:
13465159
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
FORMING CMOS WITH CLOSE PROXIMITY STRESSORS
31
Patent #:
Issue Dt:
10/08/2013
Application #:
13465486
Filing Dt:
05/07/2012
Title:
METHODS OF FORMING CMOS SEMICONDUCTOR DEVICES
32
Patent #:
Issue Dt:
08/19/2014
Application #:
13465633
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME
33
Patent #:
Issue Dt:
02/23/2016
Application #:
13465909
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
METHOD FOR INCREASING THE ROBUSTNESS OF A DOUBLE PATTERNING ROUTER USED TO MANUFACTURE INTEGRATED CIRCUIT DEVICES
34
Patent #:
Issue Dt:
04/28/2015
Application #:
13466234
Filing Dt:
05/08/2012
Publication #:
Pub Dt:
11/14/2013
Title:
HORIZONTAL EPITAXY FURNACE FOR CHANNEL SIGE FORMATION
35
Patent #:
Issue Dt:
10/28/2014
Application #:
13466895
Filing Dt:
05/08/2012
Publication #:
Pub Dt:
11/14/2013
Title:
INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE
36
Patent #:
Issue Dt:
12/25/2012
Application #:
13467385
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
08/30/2012
Title:
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
37
Patent #:
Issue Dt:
03/24/2015
Application #:
13467659
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
11/14/2013
Title:
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
38
Patent #:
Issue Dt:
03/24/2015
Application #:
13467730
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
08/30/2012
Title:
SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGIONS AND DEFECT-FREE ACTIVE SEMICONDUCTOR MATERIAL
39
Patent #:
Issue Dt:
06/03/2014
Application #:
13468083
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
40
Patent #:
Issue Dt:
07/22/2014
Application #:
13468223
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/13/2012
Title:
PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES
41
Patent #:
Issue Dt:
09/16/2014
Application #:
13468232
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/13/2012
Title:
METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
42
Patent #:
Issue Dt:
02/11/2014
Application #:
13468268
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
11/14/2013
Title:
INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL)
43
Patent #:
Issue Dt:
07/09/2013
Application #:
13468270
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
Structure and Method for Manufacturing Asymmetric Devices
44
Patent #:
Issue Dt:
12/24/2013
Application #:
13468281
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
45
Patent #:
Issue Dt:
09/03/2013
Application #:
13468307
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/06/2012
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
46
Patent #:
Issue Dt:
07/21/2015
Application #:
13468576
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
11/14/2013
Title:
PRINTED TRANSISTOR AND FABRICATION METHOD
47
Patent #:
Issue Dt:
03/24/2015
Application #:
13469220
Filing Dt:
05/11/2012
Publication #:
Pub Dt:
11/14/2013
Title:
FABRICATE SELF-FORMED NANOMETER PORE ARRAY AT WAFER SCALE FOR DNA SEQUENCING
48
Patent #:
Issue Dt:
09/15/2015
Application #:
13469386
Filing Dt:
05/11/2012
Publication #:
Pub Dt:
11/14/2013
Title:
CHIP IDENTIFICATION PATTERN AND METHOD OF FORMING
49
Patent #:
Issue Dt:
01/20/2015
Application #:
13469464
Filing Dt:
05/11/2012
Publication #:
Pub Dt:
09/06/2012
Title:
STRIPED ON-CHIP INDUCTOR
50
Patent #:
Issue Dt:
07/01/2014
Application #:
13469487
Filing Dt:
05/11/2012
Publication #:
Pub Dt:
09/06/2012
Title:
ELECTRONIC DEVICE WITH AEROGEL THERMAL ISOLATION
51
Patent #:
Issue Dt:
04/16/2013
Application #:
13469604
Filing Dt:
05/11/2012
Publication #:
Pub Dt:
08/30/2012
Title:
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
52
Patent #:
Issue Dt:
12/02/2014
Application #:
13470393
Filing Dt:
05/14/2012
Publication #:
Pub Dt:
09/06/2012
Title:
Asymmetric FinFET devices
53
Patent #:
Issue Dt:
07/28/2015
Application #:
13470454
Filing Dt:
05/14/2012
Publication #:
Pub Dt:
11/14/2013
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES WITH EMBEDDED SEMICONDUCTOR MATERIAL AS SOURCE/DRAIN REGIONS USING A REDUCED NUMBER OF SPACERS
54
Patent #:
Issue Dt:
06/16/2015
Application #:
13470620
Filing Dt:
05/14/2012
Publication #:
Pub Dt:
11/14/2013
Title:
BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
55
Patent #:
Issue Dt:
03/22/2016
Application #:
13470645
Filing Dt:
05/14/2012
Publication #:
Pub Dt:
11/14/2013
Title:
EVALUATING TRANSISTORS WITH E-BEAM INSPECTION
56
Patent #:
Issue Dt:
01/21/2014
Application #:
13471627
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
09/06/2012
Title:
SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE
57
Patent #:
Issue Dt:
08/27/2013
Application #:
13471684
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
09/06/2012
Title:
DOPANT MARKER FOR PRECISE RECESS CONTROL
58
Patent #:
Issue Dt:
03/24/2015
Application #:
13471711
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
09/06/2012
Title:
HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE
59
Patent #:
Issue Dt:
02/11/2014
Application #:
13471736
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
SUB-CIRCUIT MODELS WITH CORNER INSTANCES FOR VLSI DESIGNS
60
Patent #:
Issue Dt:
03/25/2014
Application #:
13471846
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHOD FOR FORMING A SELF-ALIGNED CONTACT OPENING BY A LATERAL ETCH
61
Patent #:
Issue Dt:
01/14/2014
Application #:
13471852
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES
62
Patent #:
Issue Dt:
04/22/2014
Application #:
13471955
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
MOS CAPACITORS WITH A FINFET PROCESS
63
Patent #:
Issue Dt:
09/03/2013
Application #:
13472044
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
12/20/2012
Title:
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
64
Patent #:
Issue Dt:
02/25/2014
Application #:
13472584
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR
65
Patent #:
Issue Dt:
08/26/2014
Application #:
13472605
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHOD AND STRUCTURE FOR FORMING FIN RESISTORS
66
Patent #:
Issue Dt:
12/30/2014
Application #:
13472674
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION
67
Patent #:
Issue Dt:
09/10/2013
Application #:
13472680
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
03/14/2013
Title:
CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES
68
Patent #:
Issue Dt:
02/17/2015
Application #:
13472747
Filing Dt:
05/16/2012
Publication #:
Pub Dt:
11/21/2013
Title:
Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate
69
Patent #:
Issue Dt:
02/18/2014
Application #:
13474090
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
06/13/2013
Title:
WAFER DICING EMPLOYING EDGE REGION UNDERFILL REMOVAL
70
Patent #:
Issue Dt:
03/22/2016
Application #:
13474257
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
09/13/2012
Title:
SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE
71
Patent #:
Issue Dt:
02/04/2014
Application #:
13474304
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
09/13/2012
Title:
ANALYZING ANTICIPATED VALUE AND EFFORT IN USING CLOUD COMPUTING TO PROCESS A SPECIFIED WORKLOAD
72
Patent #:
Issue Dt:
04/09/2013
Application #:
13474349
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
09/13/2012
Title:
SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME
73
Patent #:
Issue Dt:
12/10/2013
Application #:
13474443
Filing Dt:
05/17/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES
74
Patent #:
Issue Dt:
10/22/2013
Application #:
13474790
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
09/13/2012
Title:
TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE
75
Patent #:
Issue Dt:
12/17/2013
Application #:
13474916
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
09/13/2012
Title:
METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE
76
Patent #:
Issue Dt:
01/06/2015
Application #:
13474949
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
11/14/2013
Title:
BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
77
Patent #:
Issue Dt:
10/15/2013
Application #:
13475485
Filing Dt:
05/18/2012
Title:
RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS
78
Patent #:
Issue Dt:
02/04/2014
Application #:
13475503
Filing Dt:
05/18/2012
Publication #:
Pub Dt:
11/22/2012
Title:
LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH
79
Patent #:
Issue Dt:
12/15/2015
Application #:
13476056
Filing Dt:
05/21/2012
Publication #:
Pub Dt:
11/21/2013
Title:
VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION
80
Patent #:
Issue Dt:
03/04/2014
Application #:
13476552
Filing Dt:
05/21/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHODS OF FORMING A SILICON SEED LAYER AND LAYERS OF SILICON AND SILICON-CONTAINING MATERIAL THEREFROM
81
Patent #:
Issue Dt:
11/12/2013
Application #:
13476567
Filing Dt:
05/21/2012
Publication #:
Pub Dt:
11/21/2013
Title:
MOS CAPACITORS WITH A FINFET PROCESS
82
Patent #:
Issue Dt:
11/12/2013
Application #:
13476645
Filing Dt:
05/21/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS
83
Patent #:
Issue Dt:
03/18/2014
Application #:
13476692
Filing Dt:
05/21/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION
84
Patent #:
Issue Dt:
04/08/2014
Application #:
13476860
Filing Dt:
05/21/2012
Publication #:
Pub Dt:
11/21/2013
Title:
METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE
85
Patent #:
Issue Dt:
06/23/2015
Application #:
13477978
Filing Dt:
05/22/2012
Publication #:
Pub Dt:
11/28/2013
Title:
INDUCTOR WITH STACKED CONDUCTORS
86
Patent #:
Issue Dt:
06/02/2015
Application #:
13478080
Filing Dt:
05/22/2012
Publication #:
Pub Dt:
11/28/2013
Title:
INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES
87
Patent #:
Issue Dt:
05/26/2015
Application #:
13478154
Filing Dt:
05/23/2012
Publication #:
Pub Dt:
11/28/2013
Title:
STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETS)
88
Patent #:
Issue Dt:
02/25/2014
Application #:
13478411
Filing Dt:
05/23/2012
Publication #:
Pub Dt:
11/28/2013
Title:
FORMING FACET-LESS EPITAXY WITH A CUT MASK
89
Patent #:
Issue Dt:
02/18/2014
Application #:
13478519
Filing Dt:
05/23/2012
Publication #:
Pub Dt:
11/28/2013
Title:
SUPERIOR STABILITY OF CHARACTERISTICS OF TRANSISTORS HAVING AN EARLY FORMED HIGH-K METAL GATE
90
Patent #:
Issue Dt:
05/27/2014
Application #:
13478932
Filing Dt:
05/23/2012
Publication #:
Pub Dt:
11/28/2013
Title:
DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY
91
Patent #:
Issue Dt:
02/11/2014
Application #:
13479448
Filing Dt:
05/24/2012
Publication #:
Pub Dt:
11/28/2013
Title:
MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE
92
Patent #:
Issue Dt:
06/30/2015
Application #:
13479946
Filing Dt:
05/24/2012
Publication #:
Pub Dt:
12/06/2012
Title:
WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS
93
Patent #:
Issue Dt:
05/28/2013
Application #:
13480329
Filing Dt:
05/24/2012
Publication #:
Pub Dt:
11/08/2012
Title:
THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SPALLING
94
Patent #:
Issue Dt:
08/27/2013
Application #:
13480573
Filing Dt:
05/25/2012
Title:
CLOSED-LOOP SLEW-RATE CONTROL FOR PHASE INTERPOLATOR OPTIMIZATION
95
Patent #:
Issue Dt:
03/18/2014
Application #:
13480831
Filing Dt:
05/25/2012
Publication #:
Pub Dt:
11/28/2013
Title:
METHOD AND APPARATUS FOR SUBSTRATE-MASK ALIGNMENT
96
Patent #:
Issue Dt:
07/16/2013
Application #:
13481048
Filing Dt:
05/25/2012
Title:
BIPOLAR JUNCTION TRANSISTOR WITH EPITAXIAL CONTACTS
97
Patent #:
Issue Dt:
04/29/2014
Application #:
13481062
Filing Dt:
05/25/2012
Publication #:
Pub Dt:
11/28/2013
Title:
SPALLING UTILIZING STRESSOR LAYER PORTIONS
98
Patent #:
Issue Dt:
07/05/2016
Application #:
13482166
Filing Dt:
05/29/2012
Publication #:
Pub Dt:
12/05/2013
Title:
CONTENT ADDRESSABLE MEMORY EARLY-PREDICT LATE-CORRECT SINGLE ENDED SENSING
99
Patent #:
Issue Dt:
08/26/2014
Application #:
13482262
Filing Dt:
05/29/2012
Publication #:
Pub Dt:
09/20/2012
Title:
METHOD TO IMPROVE NUCLEATION OF MATERIALS ON GRAPHENE AND CARBON NANOTUBES
100
Patent #:
Issue Dt:
06/09/2015
Application #:
13482352
Filing Dt:
05/29/2012
Publication #:
Pub Dt:
12/05/2013
Title:
CORROSION/ETCHING PROTECTION IN INTEGRATION CIRCUIT FABRICATIONS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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