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06/16/2015
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13602118
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09/01/2012
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Pub Dt:
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01/03/2013
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Title:
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STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
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06/25/2013
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13602119
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09/01/2012
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Pub Dt:
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12/27/2012
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Title:
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METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS
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12/31/2013
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13602123
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09/01/2012
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Pub Dt:
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12/27/2012
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Title:
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MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE
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06/16/2015
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13602126
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09/01/2012
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01/03/2013
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Title:
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INTERCONNECT STRUCTURES CONTAINING A PHOTO-PATTERNABLE
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06/10/2014
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13602164
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09/02/2012
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12/27/2012
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Title:
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IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL
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08/30/2016
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13602496
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09/04/2012
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Pub Dt:
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12/27/2012
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Title:
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INTERCONNECT STRUCTURE INCLUDING A MODIFIED PHOTORESIST AS A PERMANENT INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME
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09/02/2014
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13602777
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09/04/2012
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01/02/2014
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3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS
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10/14/2014
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13602839
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09/04/2012
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Pub Dt:
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03/06/2014
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Title:
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SEMICONDUCTOR DEVICE INCORPORATING A MULTI-FUNCTION LAYER INTO GATE STACKS
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07/23/2013
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13602957
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09/04/2012
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12/27/2012
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HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS
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12/22/2015
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13603008
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09/04/2012
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12/27/2012
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LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
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11/12/2013
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13603052
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09/04/2012
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Title:
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SYSTEM AND METHOD FOR GENERATING A WIRE MODEL
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06/04/2013
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13603086
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09/04/2012
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01/03/2013
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Title:
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SOLID STATE KLYSTRON
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12/24/2013
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13603110
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09/04/2012
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12/27/2012
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Title:
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SOLID STATE KLYSTRON
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05/06/2014
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13603304
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09/04/2012
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03/06/2014
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Title:
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METHOD TO ENHANCE DOUBLE PATTERNING ROUTING EFFICIENCY
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11/04/2014
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13603513
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09/05/2012
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Pub Dt:
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03/06/2014
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Title:
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LOW RESISTIVITY GATE CONDUCTOR
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09/24/2013
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13603567
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09/05/2012
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12/27/2012
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Title:
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AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES
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02/25/2014
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13603725
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09/05/2012
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Pub Dt:
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03/06/2014
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Title:
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SELECTIVE FIN CUT PROCESS
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05/13/2014
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13603726
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09/05/2012
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Pub Dt:
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03/06/2014
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Title:
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REPLACEMENT METAL GATE SEMICONDUCTOR DEVICE FORMATION USING LOW RESISTIVITY METALS
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09/02/2014
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13603739
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09/05/2012
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Pub Dt:
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01/03/2013
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SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT
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12/30/2014
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13603869
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09/05/2012
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Pub Dt:
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12/04/2014
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Title:
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TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES
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11/19/2013
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13603872
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Filing Dt:
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09/05/2012
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Title:
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RAISED ISOLATION STRUCTURE SELF-ALIGNED TO FIN STRUCTURES
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10/14/2014
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13603892
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Filing Dt:
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09/05/2012
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Pub Dt:
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12/27/2012
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Title:
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INTEGRATED CROSS-TESTER ANALYSIS AND REAL-TIME ADAPTIVE TEST
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07/09/2013
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13603927
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09/05/2012
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Pub Dt:
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04/04/2013
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HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE
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06/16/2015
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13603944
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09/05/2012
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01/03/2013
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METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE
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11/18/2014
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13604090
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09/05/2012
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Pub Dt:
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12/27/2012
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Title:
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ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES
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12/10/2013
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13604230
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09/05/2012
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Pub Dt:
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12/27/2012
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METHOD TO EVALUATE EFFECTIVENESS OF SUBSTRATE CLEANNESS AND QUANTITY OF PIN HOLES IN AN ANTIREFLECTIVE COATING OF A SOLAR CELL
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09/17/2013
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13604340
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09/05/2012
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12/27/2012
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Title:
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MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS
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10/15/2013
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13604341
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09/05/2012
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12/27/2012
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SILICON CARRIER OPTOELECTRONIC PACKAGING
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05/26/2015
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13604363
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09/05/2012
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Pub Dt:
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12/27/2012
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Title:
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AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
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09/23/2014
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13604658
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09/06/2012
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03/06/2014
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BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER
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06/16/2015
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13604660
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09/06/2012
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Pub Dt:
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03/06/2014
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OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
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07/09/2013
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13604671
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09/06/2012
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01/03/2013
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Title:
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LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR
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09/06/2016
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13604739
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09/06/2012
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12/27/2012
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Deposition On A Nanowire Using Atomic Layer Deposition
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07/21/2015
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13604800
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09/06/2012
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03/06/2014
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Title:
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SRAM LOCAL EVALUATION AND WRITE LOGIC FOR COLUMN SELECTION
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11/05/2013
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13604814
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09/06/2012
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Title:
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CIRCUIT DESIGN WITH GROWABLE CAPACITOR ARRAYS
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12/30/2014
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13604820
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09/06/2012
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12/27/2012
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METHODS FOR CONTROLLING WAFER CURVATURE
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12/23/2014
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13604878
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09/06/2012
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Pub Dt:
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03/06/2014
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WIRE BOND SPLASH CONTAINMENT
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12/31/2013
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13604963
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09/06/2012
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08/01/2013
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SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
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10/28/2014
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13604986
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09/06/2012
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12/27/2012
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COMPREHENSIVE ANALYSIS OF QUEUE TIMES IN MICROELECTRONIC MANUFACTURING
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01/27/2015
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13604995
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09/06/2012
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03/07/2013
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AMPLIFIERS USING GATED DIODES
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01/27/2015
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13605060
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09/06/2012
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Pub Dt:
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03/06/2014
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METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES
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06/03/2014
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13605136
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09/06/2012
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12/27/2012
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FORMATION OF DIVIDERS BETWEEN GATE ENDS OF FIELD EFFECT TRANSISTOR DEVICES
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10/15/2013
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13605253
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09/06/2012
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Pub Dt:
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10/03/2013
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SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT
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07/01/2014
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13606035
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09/07/2012
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01/03/2013
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METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
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10/07/2014
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13606055
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09/07/2012
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12/27/2012
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METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY
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11/26/2013
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13606326
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09/07/2012
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01/10/2013
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ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
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10/15/2013
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13606365
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09/07/2012
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07/11/2013
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Nanowire Field Effect Transistors
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06/02/2015
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13606448
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09/07/2012
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Pub Dt:
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03/13/2014
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DEEP TRENCH CAPACITOR
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12/08/2015
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13606788
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09/07/2012
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02/07/2013
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SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION
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10/14/2014
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13606815
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09/07/2012
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12/27/2012
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ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING
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01/14/2014
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13606816
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09/07/2012
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12/27/2012
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MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS
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03/15/2016
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13606873
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09/07/2012
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02/07/2013
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FINFET FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
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05/13/2014
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13606893
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09/07/2012
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Pub Dt:
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06/20/2013
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SOI FINFET WITH RECESSED MERGED FINS AND LINER FOR ENHANCED STRESS COUPLING
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01/06/2015
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13606904
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09/07/2012
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12/27/2012
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SELF-SEALED FLUIDIC CHANNELS FOR A NANOPORE ARRAY
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05/26/2015
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13606916
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09/07/2012
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02/28/2013
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FORMATION OF METAL NANOSPHERES AND MICROSPHERES
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03/18/2014
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13606940
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09/07/2012
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Pub Dt:
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03/13/2014
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CLOCK FEATHERED SLEW RATE CONTROL SYSTEM
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01/06/2015
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13607020
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09/07/2012
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Pub Dt:
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02/28/2013
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PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS
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06/18/2013
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13607089
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09/07/2012
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02/28/2013
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Title:
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3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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13607672
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Filing Dt:
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09/08/2012
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Title:
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GERMANIUM LATERAL BIPOLAR JUNCTION TRANSISTOR
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13607674
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Filing Dt:
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09/08/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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13607678
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Filing Dt:
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09/08/2012
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Publication #:
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Pub Dt:
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10/17/2013
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Title:
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METHODOLOGIES FOR AUTOMATIC 3-D DEVICE STRUCTURE SYNTHESIS FROM CIRCUIT LAYOUTS FOR DEVICE SIMULATION
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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13607680
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Filing Dt:
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09/08/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
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Patent #:
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Issue Dt:
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10/31/2017
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Application #:
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13607741
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Filing Dt:
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09/09/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13607743
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Filing Dt:
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09/09/2012
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Publication #:
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Pub Dt:
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04/25/2013
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Title:
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THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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13607744
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Filing Dt:
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09/09/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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CAPPING COATING FOR 3D INTEGRATION APPLICATIONS
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13607856
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13607875
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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06/27/2013
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Title:
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THIN HETEREOSTRUCTURE CHANNEL DEVICE
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13607954
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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05/27/2014
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Application #:
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13608183
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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ELECTRONIC ANTI-FUSE
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13608211
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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Semiconductor plural gate lengths
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13608277
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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HYBRID PHASE-LOCKED LOOP ARCHITECTURES
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13608281
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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MULTI-MODE MULTIPLEXING USING STAGED COUPLING AND QUASI-PHASE-MATCHING
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13608314
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND STRUCTURE INCLUDING MULTIPLE ORDER RADIO FREQUENCY HARMONIC SUPRESSING REGION
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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13608409
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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Near-Infrared Absorbing Film Compositions
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Patent #:
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Issue Dt:
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08/09/2016
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Application #:
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13608455
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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ON-PRODUCT FOCUS OFFSET METROLOGY FOR USE IN SEMICONDUCTOR CHIP MANUFACTURING
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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13608706
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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High Performance Compliant Wafer Test Probe
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Patent #:
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Issue Dt:
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12/31/2013
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Application #:
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13609615
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Filing Dt:
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09/11/2012
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Title:
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FIN BIPOLAR TRANSISTORS HAVING SELF-ALIGNED COLLECTOR AND EMITTER REGIONS
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13609655
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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MEMORY DEVICE REFRESH
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Patent #:
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Issue Dt:
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09/23/2014
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Application #:
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13609668
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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METHOD OF MAKING A COPPER INTERCONNECT HAVING A BARRIER LINER OF MULTIPLE METAL LAYERS
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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13609828
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Filing Dt:
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09/11/2012
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Title:
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METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES WITH A NANOWIRE GATE STRUCTURE WHEREIN THE NANOWIRE GATE STRUCTURE IS FORMED AFTER SOURCE/DRAIN FORMATION
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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13609941
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Filing Dt:
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09/11/2012
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Title:
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METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES WITH A NANOWIRE GATE STRUCTURE WHEREIN THE NANOWIRE GATE STRUCTURE IS FORMED PRIOR TO SOURCE/DRAIN FORMATION
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Patent #:
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Issue Dt:
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07/22/2014
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Application #:
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13610158
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13610223
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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01/17/2013
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Title:
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GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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03/28/2017
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Application #:
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13610262
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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13610263
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Filing Dt:
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09/11/2012
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Title:
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METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DEPOSITION-ETCH-DEPOSITION SEQUENCE
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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13610456
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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04/04/2013
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Title:
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ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13610641
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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SILICON GERMANIUM (SIGE) HETEROJUNCTION BIPOLAR TRANSISTOR (HBT)
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Patent #:
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Issue Dt:
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07/22/2014
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Application #:
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13610991
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13611008
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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HYBRID PHASE-LOCKED LOOP ARCHITECTURES
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13611044
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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02/07/2013
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Title:
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REPLACEMENT GATE ETSOI WITH SHARP JUNCTION
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13611081
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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05/02/2013
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Title:
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NANOWIRE EFUSES
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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13611162
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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12/24/2015
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Title:
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ULTRA-SENSITIVE RADIATION DOSIMETERS
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13611182
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13611193
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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03/11/2014
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Application #:
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13611257
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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03/06/2014
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Title:
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TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13611261
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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09/26/2013
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Title:
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ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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13611335
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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07/11/2013
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Title:
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RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS
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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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13611359
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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10/31/2013
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Title:
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FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13611387
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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10/10/2013
| | | | |
Title:
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DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13611423
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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01/03/2013
| | | | |
Title:
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PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL
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