skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
06/16/2015
Application #:
13602118
Filing Dt:
09/01/2012
Publication #:
Pub Dt:
01/03/2013
Title:
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
2
Patent #:
Issue Dt:
06/25/2013
Application #:
13602119
Filing Dt:
09/01/2012
Publication #:
Pub Dt:
12/27/2012
Title:
METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS
3
Patent #:
Issue Dt:
12/31/2013
Application #:
13602123
Filing Dt:
09/01/2012
Publication #:
Pub Dt:
12/27/2012
Title:
MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE
4
Patent #:
Issue Dt:
06/16/2015
Application #:
13602126
Filing Dt:
09/01/2012
Publication #:
Pub Dt:
01/03/2013
Title:
INTERCONNECT STRUCTURES CONTAINING A PHOTO-PATTERNABLE LOW-K DIELECTRIC WITH A CURVED SIDEWALL SURFACE
5
Patent #:
Issue Dt:
06/10/2014
Application #:
13602164
Filing Dt:
09/02/2012
Publication #:
Pub Dt:
12/27/2012
Title:
IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL
6
Patent #:
Issue Dt:
08/30/2016
Application #:
13602496
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
12/27/2012
Title:
INTERCONNECT STRUCTURE INCLUDING A MODIFIED PHOTORESIST AS A PERMANENT INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME
7
Patent #:
Issue Dt:
09/02/2014
Application #:
13602777
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
01/02/2014
Title:
3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS
8
Patent #:
Issue Dt:
10/14/2014
Application #:
13602839
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
03/06/2014
Title:
SEMICONDUCTOR DEVICE INCORPORATING A MULTI-FUNCTION LAYER INTO GATE STACKS
9
Patent #:
Issue Dt:
07/23/2013
Application #:
13602957
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
12/27/2012
Title:
HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS
10
Patent #:
Issue Dt:
12/22/2015
Application #:
13603008
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
12/27/2012
Title:
LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
11
Patent #:
Issue Dt:
11/12/2013
Application #:
13603052
Filing Dt:
09/04/2012
Title:
SYSTEM AND METHOD FOR GENERATING A WIRE MODEL
12
Patent #:
Issue Dt:
06/04/2013
Application #:
13603086
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
01/03/2013
Title:
SOLID STATE KLYSTRON
13
Patent #:
Issue Dt:
12/24/2013
Application #:
13603110
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
12/27/2012
Title:
SOLID STATE KLYSTRON
14
Patent #:
Issue Dt:
05/06/2014
Application #:
13603304
Filing Dt:
09/04/2012
Publication #:
Pub Dt:
03/06/2014
Title:
METHOD TO ENHANCE DOUBLE PATTERNING ROUTING EFFICIENCY
15
Patent #:
Issue Dt:
11/04/2014
Application #:
13603513
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
03/06/2014
Title:
LOW RESISTIVITY GATE CONDUCTOR
16
Patent #:
Issue Dt:
09/24/2013
Application #:
13603567
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES
17
Patent #:
Issue Dt:
02/25/2014
Application #:
13603725
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
03/06/2014
Title:
SELECTIVE FIN CUT PROCESS
18
Patent #:
Issue Dt:
05/13/2014
Application #:
13603726
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
03/06/2014
Title:
REPLACEMENT METAL GATE SEMICONDUCTOR DEVICE FORMATION USING LOW RESISTIVITY METALS
19
Patent #:
Issue Dt:
09/02/2014
Application #:
13603739
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
01/03/2013
Title:
SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT
20
Patent #:
Issue Dt:
12/30/2014
Application #:
13603869
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/04/2014
Title:
TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES
21
Patent #:
Issue Dt:
11/19/2013
Application #:
13603872
Filing Dt:
09/05/2012
Title:
RAISED ISOLATION STRUCTURE SELF-ALIGNED TO FIN STRUCTURES
22
Patent #:
Issue Dt:
10/14/2014
Application #:
13603892
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
INTEGRATED CROSS-TESTER ANALYSIS AND REAL-TIME ADAPTIVE TEST
23
Patent #:
Issue Dt:
07/09/2013
Application #:
13603927
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
04/04/2013
Title:
HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE
24
Patent #:
Issue Dt:
06/16/2015
Application #:
13603944
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
01/03/2013
Title:
METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE
25
Patent #:
Issue Dt:
11/18/2014
Application #:
13604090
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES
26
Patent #:
Issue Dt:
12/10/2013
Application #:
13604230
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
METHOD TO EVALUATE EFFECTIVENESS OF SUBSTRATE CLEANNESS AND QUANTITY OF PIN HOLES IN AN ANTIREFLECTIVE COATING OF A SOLAR CELL
27
Patent #:
Issue Dt:
09/17/2013
Application #:
13604340
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS
28
Patent #:
Issue Dt:
10/15/2013
Application #:
13604341
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
SILICON CARRIER OPTOELECTRONIC PACKAGING
29
Patent #:
Issue Dt:
05/26/2015
Application #:
13604363
Filing Dt:
09/05/2012
Publication #:
Pub Dt:
12/27/2012
Title:
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
30
Patent #:
Issue Dt:
09/23/2014
Application #:
13604658
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
03/06/2014
Title:
BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER
31
Patent #:
Issue Dt:
06/16/2015
Application #:
13604660
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
03/06/2014
Title:
OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
32
Patent #:
Issue Dt:
07/09/2013
Application #:
13604671
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
01/03/2013
Title:
LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES TO ACHIEVE A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE, A METHOD OF FORMING THE TRANSISTOR AND A PROGRAM STORAGE DEVICE FOR DESIGNING THE TRANSISTOR
33
Patent #:
Issue Dt:
09/06/2016
Application #:
13604739
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
12/27/2012
Title:
Deposition On A Nanowire Using Atomic Layer Deposition
34
Patent #:
Issue Dt:
07/21/2015
Application #:
13604800
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
03/06/2014
Title:
SRAM LOCAL EVALUATION AND WRITE LOGIC FOR COLUMN SELECTION
35
Patent #:
Issue Dt:
11/05/2013
Application #:
13604814
Filing Dt:
09/06/2012
Title:
CIRCUIT DESIGN WITH GROWABLE CAPACITOR ARRAYS
36
Patent #:
Issue Dt:
12/30/2014
Application #:
13604820
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
12/27/2012
Title:
METHODS FOR CONTROLLING WAFER CURVATURE
37
Patent #:
Issue Dt:
12/23/2014
Application #:
13604878
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
03/06/2014
Title:
WIRE BOND SPLASH CONTAINMENT
38
Patent #:
Issue Dt:
12/31/2013
Application #:
13604963
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
08/01/2013
Title:
SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
39
Patent #:
Issue Dt:
10/28/2014
Application #:
13604986
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
12/27/2012
Title:
COMPREHENSIVE ANALYSIS OF QUEUE TIMES IN MICROELECTRONIC MANUFACTURING
40
Patent #:
Issue Dt:
01/27/2015
Application #:
13604995
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
03/07/2013
Title:
AMPLIFIERS USING GATED DIODES
41
Patent #:
Issue Dt:
01/27/2015
Application #:
13605060
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
03/06/2014
Title:
METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES
42
Patent #:
Issue Dt:
06/03/2014
Application #:
13605136
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
12/27/2012
Title:
FORMATION OF DIVIDERS BETWEEN GATE ENDS OF FIELD EFFECT TRANSISTOR DEVICES
43
Patent #:
Issue Dt:
10/15/2013
Application #:
13605253
Filing Dt:
09/06/2012
Publication #:
Pub Dt:
10/03/2013
Title:
SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT
44
Patent #:
Issue Dt:
07/01/2014
Application #:
13606035
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
01/03/2013
Title:
METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
45
Patent #:
Issue Dt:
10/07/2014
Application #:
13606055
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
12/27/2012
Title:
METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY
46
Patent #:
Issue Dt:
11/26/2013
Application #:
13606326
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
01/10/2013
Title:
ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
47
Patent #:
Issue Dt:
10/15/2013
Application #:
13606365
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
07/11/2013
Title:
Nanowire Field Effect Transistors
48
Patent #:
Issue Dt:
06/02/2015
Application #:
13606448
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
03/13/2014
Title:
DEEP TRENCH CAPACITOR
49
Patent #:
Issue Dt:
12/08/2015
Application #:
13606788
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
02/07/2013
Title:
SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION
50
Patent #:
Issue Dt:
10/14/2014
Application #:
13606815
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
12/27/2012
Title:
ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING
51
Patent #:
Issue Dt:
01/14/2014
Application #:
13606816
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
12/27/2012
Title:
MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS
52
Patent #:
Issue Dt:
03/15/2016
Application #:
13606873
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
02/07/2013
Title:
FINFET FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
53
Patent #:
Issue Dt:
05/13/2014
Application #:
13606893
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
06/20/2013
Title:
SOI FINFET WITH RECESSED MERGED FINS AND LINER FOR ENHANCED STRESS COUPLING
54
Patent #:
Issue Dt:
01/06/2015
Application #:
13606904
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
12/27/2012
Title:
SELF-SEALED FLUIDIC CHANNELS FOR A NANOPORE ARRAY
55
Patent #:
Issue Dt:
05/26/2015
Application #:
13606916
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
02/28/2013
Title:
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
56
Patent #:
Issue Dt:
03/18/2014
Application #:
13606940
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
03/13/2014
Title:
CLOCK FEATHERED SLEW RATE CONTROL SYSTEM
57
Patent #:
Issue Dt:
01/06/2015
Application #:
13607020
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
02/28/2013
Title:
PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STACK OF INTEGRATED CIRCUITS
58
Patent #:
Issue Dt:
06/18/2013
Application #:
13607089
Filing Dt:
09/07/2012
Publication #:
Pub Dt:
02/28/2013
Title:
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING
59
Patent #:
Issue Dt:
10/15/2013
Application #:
13607672
Filing Dt:
09/08/2012
Title:
GERMANIUM LATERAL BIPOLAR JUNCTION TRANSISTOR
60
Patent #:
Issue Dt:
07/01/2014
Application #:
13607674
Filing Dt:
09/08/2012
Publication #:
Pub Dt:
01/03/2013
Title:
TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
61
Patent #:
Issue Dt:
11/05/2013
Application #:
13607678
Filing Dt:
09/08/2012
Publication #:
Pub Dt:
10/17/2013
Title:
METHODOLOGIES FOR AUTOMATIC 3-D DEVICE STRUCTURE SYNTHESIS FROM CIRCUIT LAYOUTS FOR DEVICE SIMULATION
62
Patent #:
Issue Dt:
04/01/2014
Application #:
13607680
Filing Dt:
09/08/2012
Publication #:
Pub Dt:
12/27/2012
Title:
SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
63
Patent #:
Issue Dt:
10/31/2017
Application #:
13607741
Filing Dt:
09/09/2012
Publication #:
Pub Dt:
12/27/2012
Title:
HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS
64
Patent #:
Issue Dt:
10/21/2014
Application #:
13607743
Filing Dt:
09/09/2012
Publication #:
Pub Dt:
04/25/2013
Title:
THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS
65
Patent #:
Issue Dt:
12/16/2014
Application #:
13607744
Filing Dt:
09/09/2012
Publication #:
Pub Dt:
12/27/2012
Title:
CAPPING COATING FOR 3D INTEGRATION APPLICATIONS
66
Patent #:
Issue Dt:
10/07/2014
Application #:
13607856
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
03/13/2014
Title:
SELF-ALIGNED CONTACTS
67
Patent #:
Issue Dt:
07/28/2015
Application #:
13607875
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
06/27/2013
Title:
THIN HETEREOSTRUCTURE CHANNEL DEVICE
68
Patent #:
Issue Dt:
10/07/2014
Application #:
13607954
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
03/13/2014
Title:
FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
69
Patent #:
Issue Dt:
05/27/2014
Application #:
13608183
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
03/13/2014
Title:
ELECTRONIC ANTI-FUSE
70
Patent #:
Issue Dt:
08/12/2014
Application #:
13608211
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
03/13/2014
Title:
Semiconductor plural gate lengths
71
Patent #:
Issue Dt:
04/22/2014
Application #:
13608277
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
03/13/2014
Title:
HYBRID PHASE-LOCKED LOOP ARCHITECTURES
72
Patent #:
Issue Dt:
05/13/2014
Application #:
13608281
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
12/27/2012
Title:
MULTI-MODE MULTIPLEXING USING STAGED COUPLING AND QUASI-PHASE-MATCHING
73
Patent #:
Issue Dt:
07/23/2013
Application #:
13608314
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
01/03/2013
Title:
SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND STRUCTURE INCLUDING MULTIPLE ORDER RADIO FREQUENCY HARMONIC SUPRESSING REGION
74
Patent #:
Issue Dt:
11/19/2013
Application #:
13608409
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
01/03/2013
Title:
Near-Infrared Absorbing Film Compositions
75
Patent #:
Issue Dt:
08/09/2016
Application #:
13608455
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
03/13/2014
Title:
ON-PRODUCT FOCUS OFFSET METROLOGY FOR USE IN SEMICONDUCTOR CHIP MANUFACTURING
76
Patent #:
Issue Dt:
05/10/2016
Application #:
13608706
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
12/27/2012
Title:
High Performance Compliant Wafer Test Probe
77
Patent #:
Issue Dt:
12/31/2013
Application #:
13609615
Filing Dt:
09/11/2012
Title:
FIN BIPOLAR TRANSISTORS HAVING SELF-ALIGNED COLLECTOR AND EMITTER REGIONS
78
Patent #:
Issue Dt:
06/09/2015
Application #:
13609655
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
03/13/2014
Title:
MEMORY DEVICE REFRESH
79
Patent #:
Issue Dt:
09/23/2014
Application #:
13609668
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
01/03/2013
Title:
METHOD OF MAKING A COPPER INTERCONNECT HAVING A BARRIER LINER OF MULTIPLE METAL LAYERS
80
Patent #:
Issue Dt:
09/24/2013
Application #:
13609828
Filing Dt:
09/11/2012
Title:
METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES WITH A NANOWIRE GATE STRUCTURE WHEREIN THE NANOWIRE GATE STRUCTURE IS FORMED AFTER SOURCE/DRAIN FORMATION
81
Patent #:
Issue Dt:
11/12/2013
Application #:
13609941
Filing Dt:
09/11/2012
Title:
METHODS OF FORMING 3-D SEMICONDUCTOR DEVICES WITH A NANOWIRE GATE STRUCTURE WHEREIN THE NANOWIRE GATE STRUCTURE IS FORMED PRIOR TO SOURCE/DRAIN FORMATION
82
Patent #:
Issue Dt:
07/22/2014
Application #:
13610158
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
03/13/2014
Title:
SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION
83
Patent #:
Issue Dt:
03/18/2014
Application #:
13610223
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
01/17/2013
Title:
GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
84
Patent #:
Issue Dt:
03/28/2017
Application #:
13610262
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
03/13/2014
Title:
EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING
85
Patent #:
Issue Dt:
12/10/2013
Application #:
13610263
Filing Dt:
09/11/2012
Title:
METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DEPOSITION-ETCH-DEPOSITION SEQUENCE
86
Patent #:
Issue Dt:
02/25/2014
Application #:
13610456
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
04/04/2013
Title:
ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS
87
Patent #:
Issue Dt:
10/07/2014
Application #:
13610641
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
01/03/2013
Title:
SILICON GERMANIUM (SIGE) HETEROJUNCTION BIPOLAR TRANSISTOR (HBT)
88
Patent #:
Issue Dt:
07/22/2014
Application #:
13610991
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
03/13/2014
Title:
SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION
89
Patent #:
Issue Dt:
04/22/2014
Application #:
13611008
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
03/13/2014
Title:
HYBRID PHASE-LOCKED LOOP ARCHITECTURES
90
Patent #:
Issue Dt:
03/18/2014
Application #:
13611044
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
02/07/2013
Title:
REPLACEMENT GATE ETSOI WITH SHARP JUNCTION
91
Patent #:
Issue Dt:
08/26/2014
Application #:
13611081
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
05/02/2013
Title:
NANOWIRE EFUSES
92
Patent #:
Issue Dt:
08/02/2016
Application #:
13611162
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
12/24/2015
Title:
ULTRA-SENSITIVE RADIATION DOSIMETERS
93
Patent #:
Issue Dt:
03/24/2015
Application #:
13611182
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
03/13/2014
Title:
SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS
94
Patent #:
Issue Dt:
05/06/2014
Application #:
13611193
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
01/03/2013
Title:
METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
95
Patent #:
Issue Dt:
03/11/2014
Application #:
13611257
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
03/06/2014
Title:
TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES
96
Patent #:
Issue Dt:
02/24/2015
Application #:
13611261
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
09/26/2013
Title:
ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS
97
Patent #:
Issue Dt:
03/17/2015
Application #:
13611335
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
07/11/2013
Title:
RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS
98
Patent #:
Issue Dt:
09/27/2016
Application #:
13611359
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
10/31/2013
Title:
FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING
99
Patent #:
Issue Dt:
07/21/2015
Application #:
13611387
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
10/10/2013
Title:
DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP
100
Patent #:
Issue Dt:
04/22/2014
Application #:
13611423
Filing Dt:
09/12/2012
Publication #:
Pub Dt:
01/03/2013
Title:
PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

Search Results as of: 05/22/2024 04:20 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT