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07/14/2015
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13664873
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10/31/2012
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Pub Dt:
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05/01/2014
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Title:
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BULK FINFET WITH PUNCHTHROUGH STOPPER REGION AND METHOD OF FABRICATION
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06/16/2015
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13665140
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Filing Dt:
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10/31/2012
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Pub Dt:
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05/01/2014
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Title:
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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09/30/2014
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13665276
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Filing Dt:
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10/31/2012
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Pub Dt:
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05/01/2014
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Title:
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HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS
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07/01/2014
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13665315
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS
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12/24/2013
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13665334
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Filing Dt:
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10/31/2012
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Title:
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Techniques for Fabricating Janus MEMS Transistors
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05/13/2014
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13666031
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11/01/2012
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05/01/2014
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Title:
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DUAL GATE FINFET DEVICES
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03/24/2015
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13666214
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11/01/2012
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Pub Dt:
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03/07/2013
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Title:
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TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS
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01/14/2014
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13666484
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11/01/2012
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03/07/2013
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Title:
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IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES
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08/11/2015
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13667384
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11/02/2012
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Pub Dt:
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05/08/2014
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Title:
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FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
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01/12/2016
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13667389
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11/02/2012
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Pub Dt:
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05/08/2014
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Title:
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FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX LATERAL EPITAXIAL REALIGNMENT OF DEPOSITED NON-CRYSTALLINE FILM ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
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03/18/2014
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13667657
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11/02/2012
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Pub Dt:
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03/07/2013
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Title:
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COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS
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Issue Dt:
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01/07/2014
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13668401
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11/05/2012
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Pub Dt:
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12/12/2013
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Title:
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SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS
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07/01/2014
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13668869
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11/05/2012
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05/08/2014
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Title:
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MAGNETORESISTIVE RANDOM ACCESS MEMORY
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Issue Dt:
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06/16/2015
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13669627
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11/06/2012
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Pub Dt:
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05/08/2014
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Title:
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CLEANING COMPOSITION AND PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
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02/11/2014
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13669651
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Filing Dt:
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11/06/2012
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Title:
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PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
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03/24/2015
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13669891
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11/06/2012
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Pub Dt:
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05/08/2014
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Title:
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MAPPING DENSITY AND TEMPERATURE OF A CHIP, IN SITU
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11/15/2016
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13670251
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11/06/2012
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Pub Dt:
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05/08/2014
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Title:
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METAL GATE STRUCTURE FOR MIDGAP SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME
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Issue Dt:
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08/26/2014
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13670566
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Filing Dt:
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11/07/2012
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Pub Dt:
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05/08/2014
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Title:
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FABRICATION OF REVERSE SHALLOW TRENCH ISOLATION STRUCTURES WITH SUPER-STEEP RETROGRADE WELLS
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Issue Dt:
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03/18/2014
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13670605
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Filing Dt:
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11/07/2012
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Title:
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METHODS OF FORMING FINS AND ISOLATION REGIONS ON A FINFET SEMICONDUCTOR DEVICE
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08/19/2014
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13670674
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11/07/2012
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Pub Dt:
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05/08/2014
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Title:
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PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
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Issue Dt:
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07/08/2014
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13670694
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Filing Dt:
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11/07/2012
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Pub Dt:
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05/08/2014
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Title:
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ENHANCED CAPTURE PADS FOR THROUGH SEMICONDUCTOR VIAS
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08/12/2014
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13670711
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11/07/2012
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Pub Dt:
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05/08/2014
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Title:
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COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME
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Issue Dt:
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09/16/2014
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13670748
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11/07/2012
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Pub Dt:
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05/08/2014
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Title:
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ROBUST REPLACEMENT GATE INTEGRATION
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Issue Dt:
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07/01/2014
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13670768
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Filing Dt:
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11/07/2012
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Publication #:
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Pub Dt:
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05/08/2014
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Title:
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METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET
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Issue Dt:
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08/06/2013
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13670880
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Filing Dt:
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11/07/2012
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Title:
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FINFET ALIGNMENT STRUCTURES USING A DOUBLE TRENCH FLOW
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Issue Dt:
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03/25/2014
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13670921
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Filing Dt:
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11/07/2012
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Title:
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SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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Issue Dt:
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08/27/2013
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13671098
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Filing Dt:
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11/07/2012
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Title:
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WAFER-TO-WAFER PROCESS FOR MANUFACTURING A STACKED STRUCTURE
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Issue Dt:
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01/21/2014
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13671186
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Filing Dt:
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11/07/2012
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Title:
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SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
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Issue Dt:
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10/14/2014
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13671226
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11/07/2012
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Pub Dt:
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05/08/2014
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Title:
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METHOD FOR SELECTIVELY MODELING NARROW-WIDTH STACKED DEVICE PERFORMANCE
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01/13/2015
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13671605
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11/08/2012
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05/08/2014
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Title:
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STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
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Issue Dt:
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10/21/2014
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13671776
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11/08/2012
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Pub Dt:
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05/01/2014
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Title:
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Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
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Issue Dt:
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07/08/2014
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13671940
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11/08/2012
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Pub Dt:
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05/08/2014
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Title:
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICE
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08/20/2013
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13672040
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11/08/2012
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Pub Dt:
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03/14/2013
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Title:
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HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
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11/15/2016
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13672751
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11/09/2012
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05/16/2013
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Title:
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MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE
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06/16/2015
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13672770
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11/09/2012
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05/15/2014
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Title:
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PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
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Issue Dt:
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04/28/2015
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13672925
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11/09/2012
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05/01/2014
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DUAL GATE FINFET DEVICES
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02/09/2016
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13673262
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11/09/2012
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Pub Dt:
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05/15/2014
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Title:
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MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS
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09/01/2015
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13673549
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11/09/2012
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05/15/2014
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Title:
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INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS WITH INTERLAYER DIELECTRIC PROTECTION
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02/03/2015
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13674142
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11/12/2012
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Pub Dt:
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05/15/2014
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Title:
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METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS
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09/24/2013
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13675442
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11/13/2012
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05/16/2013
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PROTECTIVE TREATMENT FOR POROUS MATERIALS
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11/17/2015
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13676063
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11/13/2012
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Pub Dt:
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05/15/2014
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FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN
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03/25/2014
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13676174
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11/14/2012
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03/21/2013
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Title:
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CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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01/19/2016
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13676412
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11/14/2012
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Pub Dt:
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05/15/2014
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Title:
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SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE
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05/26/2015
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13676483
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11/14/2012
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Pub Dt:
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05/15/2014
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Title:
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REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE
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Issue Dt:
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11/25/2014
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13676575
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11/14/2012
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Pub Dt:
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05/15/2014
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REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE
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09/09/2014
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13676817
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11/14/2012
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Pub Dt:
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05/15/2014
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Title:
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COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
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02/11/2014
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13677373
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Filing Dt:
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11/15/2012
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Title:
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ELASTIC MODULUS MAPPING OF AN INTEGRATED CIRCUIT CHIP IN A CHIP/DEVICE PACKAGE
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07/19/2016
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13677542
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11/15/2012
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04/17/2014
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System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
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06/16/2015
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13677610
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11/15/2012
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Pub Dt:
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05/15/2014
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ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES
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Issue Dt:
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09/23/2014
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13677647
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11/15/2012
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Pub Dt:
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05/15/2014
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CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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01/07/2014
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13677863
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11/15/2012
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SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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12/08/2015
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13677908
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11/15/2012
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05/01/2014
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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06/02/2015
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13677954
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11/15/2012
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05/15/2014
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DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
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08/04/2015
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13677997
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11/15/2012
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Pub Dt:
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05/15/2014
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SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
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02/24/2015
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13678011
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11/15/2012
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Pub Dt:
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05/15/2014
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Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SEMICONDUCTIVE RESISTOR STRUCTURES IN A FINFET ARCHITECTURE
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13678054
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Filing Dt:
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11/15/2012
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Publication #:
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Pub Dt:
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05/15/2014
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13678111
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Filing Dt:
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11/15/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13678124
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Filing Dt:
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11/15/2012
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Publication #:
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Pub Dt:
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05/15/2014
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Title:
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SOURCE AND DRAIN DOPING USING DOPED RAISED SOURCE AND DRAIN REGIONS
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13679222
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Filing Dt:
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11/16/2012
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Title:
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STRAINED SIGE NANOWIRE HAVING (111)-ORIENTED SIDEWALLS
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13679284
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Filing Dt:
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11/16/2012
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Publication #:
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Pub Dt:
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05/22/2014
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Title:
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LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13679357
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Filing Dt:
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11/16/2012
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Publication #:
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Pub Dt:
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03/21/2013
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Title:
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SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
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Patent #:
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Issue Dt:
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09/02/2014
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Application #:
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13681761
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Filing Dt:
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11/20/2012
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Publication #:
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Pub Dt:
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05/22/2014
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Title:
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DENSE FINFET SRAM
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13682056
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Filing Dt:
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11/20/2012
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Publication #:
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Pub Dt:
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05/22/2014
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Title:
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POLYGON RECOVERY FOR VLSI MASK CORRECTION
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Patent #:
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Issue Dt:
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11/17/2015
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Application #:
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13682331
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Filing Dt:
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11/20/2012
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Publication #:
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Pub Dt:
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05/22/2014
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Title:
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
|
05/06/2014
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Application #:
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13682769
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
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05/22/2014
| | | | |
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Title:
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FINFET FORMATION USING DOUBLE PATTERNING MEMORIZATION
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13682771
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Filing Dt:
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11/21/2012
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Title:
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USE OF POLARIZATION AND COMPOSITE ILLUMINATION SOURCE FOR ADVANCED OPTICAL LITHOGRAPHY
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Patent #:
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Issue Dt:
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04/26/2016
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Application #:
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13683508
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
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05/22/2014
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Title:
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POWER-SCALABLE SKEW COMPENSATION IN SOURCE-SYNCHRONOUS PARALLEL INTERFACES
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Patent #:
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Issue Dt:
|
03/24/2015
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Application #:
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13684818
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Filing Dt:
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11/26/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
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Title:
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FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13684842
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Filing Dt:
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11/26/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
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Title:
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DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13684869
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Filing Dt:
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11/26/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13685733
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
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Title:
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Finfet Semiconductor Device Having Increased Gate Height Control
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Patent #:
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Issue Dt:
|
04/15/2014
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Application #:
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13685735
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Filing Dt:
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11/27/2012
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Title:
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LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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13685779
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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13686203
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
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Title:
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TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS
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Patent #:
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Issue Dt:
|
10/14/2014
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Application #:
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13686263
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
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04/04/2013
| | | | |
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Title:
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METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13686377
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13686422
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Filing Dt:
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11/27/2012
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Publication #:
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Pub Dt:
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04/11/2013
| | | | |
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Title:
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ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13686954
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13686969
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
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Title:
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DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
|
06/03/2014
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Application #:
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13687218
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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04/11/2013
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Title:
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Ball Grid Array with Improved Single-Ended and Differential Signal Performance
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13687240
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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13687314
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/15/2014
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Title:
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CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13687355
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
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Title:
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES
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Patent #:
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Issue Dt:
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09/09/2014
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Application #:
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13687877
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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04/04/2013
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Title:
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RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13688259
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13688595
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Filing Dt:
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11/29/2012
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Title:
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INTEGRATED CIRCUIT HAVING LOCAL MAXIMUM OPERATING VOLTAGE
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13689044
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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ISOLATING FAILING LATCHES USING A LOGIC BUILT-IN SELF-TEST
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13689052
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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05/08/2014
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Title:
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MAGNETORESISTIVE RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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13689090
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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LIGHT ACTIVATED TEST CONNECTIONS
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Patent #:
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Issue Dt:
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02/10/2015
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Application #:
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13689437
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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05/29/2014
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Title:
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STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13689838
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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HETEROJUNCTION BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
|
04/08/2014
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Application #:
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13689839
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Filing Dt:
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11/30/2012
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Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE DEVICE CONTACTS
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Patent #:
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Issue Dt:
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07/15/2014
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Application #:
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13689844
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE METAL GATE STRUCTURES
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Patent #:
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Issue Dt:
|
01/06/2015
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Application #:
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13689924
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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UNIFORM FINFET GATE HEIGHT
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Patent #:
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Issue Dt:
|
09/09/2014
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Application #:
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13689948
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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UNIFORM FINFET GATE HEIGHT
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Patent #:
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Issue Dt:
|
02/17/2015
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Application #:
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13689979
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13689992
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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01/16/2014
| | | | |
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Title:
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WORK FUNCTION ADJUSTMENT IN A HIGH-K GATE ELECTRODE STRUCTURE AFTER TRANSISTOR FABRICATION BY USING LANTHANUM
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13690209
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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TECHNIQUES FOR ROUTING SIGNAL WIRES IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13690240
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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Semiconductor Device Having SSOI Substrate with Relaxed Tensile Stress
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13690867
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH REPLACEMENT METAL GATE AND METHOD FOR SELECTIVE DEPOSITION OF MATERIAL FOR REPLACEMENT METAL GATE
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