|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13691129
|
Filing Dt:
|
11/30/2012
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
MULTI COMPONENT DIELECTRIC LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13692069
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
INDUCING CHANNEL STRESS IN SEMICONDUCTOR-ON-INSULATOR DEVICES BY BASE SUBSTRATE OXIDATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13692369
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13692603
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
13693094
|
Filing Dt:
|
12/04/2012
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A GATE FORMED ON A UNIFORM SURFACE AND METHOD FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13693285
|
Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13693627
|
Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
ASYMMETRIC TEMPLATES FOR FORMING NON-PERIODIC PATTERNS USING DIRECTES SELF-ASSEMBLY MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13693749
|
Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
FAR BACK END OF THE LINE STACK ENCAPSULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13705261
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13705300
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
DYNAMICALLY LIMITING ENERGY CONSUMED BY COOLING APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13705477
|
Filing Dt:
|
12/05/2012
|
Title:
|
Finfet eDram Strap Connection Structure
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13705717
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13705920
|
Filing Dt:
|
12/05/2012
|
Title:
|
GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
13707003
|
Filing Dt:
|
12/06/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13707058
|
Filing Dt:
|
12/06/2012
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13708126
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13708499
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13708531
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
BULK FINFET WITH SUPER STEEP RETROGRADE WELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13708988
|
Filing Dt:
|
12/08/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13709095
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13709397
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
METHOD OF FORMING SELF-ASSEMBLED PATTERNS USING BLOCK COPOLYMERS, AND ARTICLES THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13709541
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DOUBLE SIDEWALL IMAGE TRANSFER PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13709662
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13709748
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
VECTORIZATION OF BIT-LEVEL NETLISTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13710498
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE RESOLUTION ENHANCEMENT BY ETCHING MULTIPLE SIDES OF A MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13710551
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13710561
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13710575
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13710616
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONTROLLED APPLICATION OF OERSTED FIELD TO MAGNETIC MEMORY STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13710710
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
Automated Fault and Recovery System
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13710953
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13711813
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHODS OF FORMING BULK FINFET SEMICONDUCTOR DEVICES BY PERFORMING A LINER RECESSING PROCESS TO DEFINE FIN HEIGHTS AND FINFET DEVICES WITH SUCH A RECESSED LINER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13712234
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
HIGH DENSITY SERIAL CAPACITOR DEVICE AND METHODS OF MAKING SUCH A CAPACITOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13712567
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
EFFICIENT USE OF MIRRORED STORAGE CLOUDS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13713085
|
Filing Dt:
|
12/13/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING A SIDEWALL SPACER HAVING A GENERALLY TRIANGULAR SHAPE AND A SEMICONDUCTOR DEVICE HAVING SUCH A SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13713759
|
Filing Dt:
|
12/13/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
QUANTUM CIRCUIT WITHIN WAVEGUIDE-BEYOND-CUTOFF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13714049
|
Filing Dt:
|
12/13/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SILICIDE CONTACTS ON NON-PLANAR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13714404
|
Filing Dt:
|
12/14/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE RESISTANT DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13716686
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
13716693
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13716731
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
13716758
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING FINS FOR A FINFET DEVICE WHEREIN THE FINS HAVE A HIGH GERMANIUM CONTENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13717079
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
THERMAL SPIN TORQURE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13717235
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13717701
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13717816
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
LOCALLY OPTIMIZED COLORING FOR CLEANING LITHOGRAPHIC HOTSPOTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13718158
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES HAVING CONDUCTIVE CONTACTS POSITIONED THEREBETWEEN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13718346
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13718657
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
POWER MANAGEMENT SRAM WRITE BIT LINE DRIVE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13718748
|
Filing Dt:
|
12/18/2012
|
Title:
|
FIELD-EFFECT INTER-DIGITATED BACK CONTACT PHOTOVOLTAIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13718767
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13719408
|
Filing Dt:
|
12/19/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
CHANGING RESONANT CLOCK MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13719965
|
Filing Dt:
|
12/19/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
PIEZOELECTRONIC MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13721991
|
Filing Dt:
|
12/20/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
PACKAGING STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13723514
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR-BASED BIO SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13725191
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
PHOTOMASK SETS FOR FABRICATING SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13725837
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
PRECISION POLYSILICON RESISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13726732
|
Filing Dt:
|
12/26/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
OPTIMIZING LITHOGRAPHIC PROCESSES USING LASER ANNEALING TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13727580
|
Filing Dt:
|
12/26/2012
|
Publication #:
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Pub Dt:
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06/05/2014
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Title:
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RECONFIGURABLE SWITCHED-CAPACITOR VOLTAGE CONVERTER CIRCUIT, INTEGRATED CIRCUIT (IC) CHIP INCLUDING THE CIRCUIT AND METHOD OF SWITCHING VOLTAGE ON CHIP
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Patent #:
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Issue Dt:
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05/20/2014
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Application #:
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13728438
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Filing Dt:
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12/27/2012
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Title:
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METHODS OF FORMING A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL STRUCTURE
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Patent #:
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Issue Dt:
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01/31/2017
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Application #:
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13729180
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Filing Dt:
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12/28/2012
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
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INTEGRATION OF Ru WET ETCH AND CMP FOR BEOL INTERCONNECTS WITH Ru LAYER
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Patent #:
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Issue Dt:
|
08/04/2015
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Application #:
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13729207
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Filing Dt:
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12/28/2012
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
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BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS
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Patent #:
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Issue Dt:
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11/24/2015
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Application #:
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13729843
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Filing Dt:
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12/28/2012
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
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METHODS OF USING A TRENCH SALICIDE ROUTING LAYER
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13730171
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Filing Dt:
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12/28/2012
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
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ASYMMETRIC RETICLE HEATING OF MULTILAYER RETICLES ELIMINATED BY DUMMY EXPOSURES AND RELATED METHODS
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13732455
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
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CONCURRENTLY FORMING NFET AND PFET GATE DIELECTRIC LAYERS
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13732466
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
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MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE
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Patent #:
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|
Issue Dt:
|
03/15/2016
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Application #:
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13732482
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
| | | | |
Title:
|
LOW-VOLTAGE IC TEST FOR DEFECT SCREENING
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13732494
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
|
07/03/2014
| | | | |
Title:
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INTERGRATING A SILICON PHOTONICS PHOTODETECTOR WITH CMOS DEVICES
|
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Patent #:
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|
Issue Dt:
|
12/06/2016
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Application #:
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13732708
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Filing Dt:
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01/02/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
SYSTEMS AND METHODS FOR SEMICONDUCTOR LINE SCRIBE LINE CENTERING
|
|
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Patent #:
|
|
Issue Dt:
|
02/23/2016
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Application #:
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13732713
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Filing Dt:
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01/02/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
COMPENSATED IMPEDANCE CALIBRATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
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Application #:
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13732806
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Filing Dt:
|
01/02/2013
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Publication #:
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Pub Dt:
|
05/30/2013
| | | | |
Title:
|
BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES
|
|
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Patent #:
|
|
Issue Dt:
|
04/12/2016
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Application #:
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13732825
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Filing Dt:
|
01/02/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
DUAL DAMASCENE STRUCTURE WITH LINER
|
|
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Patent #:
|
|
Issue Dt:
|
10/06/2015
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Application #:
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13732859
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Filing Dt:
|
01/02/2013
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Publication #:
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Pub Dt:
|
06/06/2013
| | | | |
Title:
|
SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2017
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Application #:
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13732932
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Filing Dt:
|
01/02/2013
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Publication #:
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Pub Dt:
|
07/03/2014
| | | | |
Title:
|
MULTIPLE MANUFACTURING LINE QUALIFICATION
|
|
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Patent #:
|
|
Issue Dt:
|
04/07/2015
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Application #:
|
13732954
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Filing Dt:
|
01/02/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
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Application #:
|
13732989
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Filing Dt:
|
01/02/2013
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Title:
|
SPARE CELL INSERTION BASED ON REACHABLE STATE ANALYSIS
|
|
|
Patent #:
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|
Issue Dt:
|
07/15/2014
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Application #:
|
13733016
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Filing Dt:
|
01/02/2013
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Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
SOFT PIN INSERTION DURING PHYSICAL DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
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Application #:
|
13733182
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Filing Dt:
|
01/03/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
ACID-STRIPPABLE SILICON-CONTAINING ANTIREFLECTIVE COATING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13733243
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Filing Dt:
|
01/03/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
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Application #:
|
13733248
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Filing Dt:
|
01/03/2013
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Publication #:
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Pub Dt:
|
07/03/2014
| | | | |
Title:
|
TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
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Application #:
|
13733282
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Filing Dt:
|
01/03/2013
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Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
GATE ELECTRODE(S) AND CONTACT STRUCTURE(S), AND METHODS OF FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
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Application #:
|
13733404
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Filing Dt:
|
01/03/2013
|
Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
NANOPORE SENSOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
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Application #:
|
13733431
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Filing Dt:
|
01/03/2013
|
Publication #:
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|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
PLANNING ECONOMIC ENERGY DISPATCH IN ELECTRICAL GRID UNDER UNCERTAINTY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2017
|
Application #:
|
13733507
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Filing Dt:
|
01/03/2013
|
Publication #:
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|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
HIGH POWER RADIO FREQUENCY (RF) IN-LINE WAFER TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
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Application #:
|
13733973
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Filing Dt:
|
01/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
TWO PHASE SEARCH CONTENT ADDRESSABLE MEMORY WITH POWER-GATED MAIN-SEARCH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13734075
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Filing Dt:
|
01/04/2013
|
Publication #:
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|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
MEASURING DIELECTRIC BREAKDOWN IN A DYNAMIC MODE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
13734357
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Filing Dt:
|
01/04/2013
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Publication #:
|
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Pub Dt:
|
07/10/2014
| | | | |
Title:
|
FOUNDRY PRODUCTION PLANNING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
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Application #:
|
13734364
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Filing Dt:
|
01/04/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
|
DESIGN STRUCTURE FOR AN INDUCTOR-CAPACITOR VOLTAGE-CONTROLLED OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13734436
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Filing Dt:
|
01/04/2013
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Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13734499
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Filing Dt:
|
01/04/2013
|
Publication #:
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|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13734501
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Filing Dt:
|
01/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
THERMAL DISSIPATIVE RETRACTABLE FLEX ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
13734524
|
Filing Dt:
|
01/04/2013
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13735314
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
Catalytic Etch With Magnetic Direction Control
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13735315
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13735392
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13735470
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
RETICLE CARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13736111
|
Filing Dt:
|
01/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
METHOD OF FORMING FINFET OF VARIABLE CHANNEL WIDTH
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13736183
|
Filing Dt:
|
01/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13736189
|
Filing Dt:
|
01/08/2013
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
MEMORY CELL WITH POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13736505
|
Filing Dt:
|
01/08/2013
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING
|
|