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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10643799
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Filing Dt:
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08/18/2003
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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METHOD AND PLATFORM FOR INTEGRATED PHYSICAL VERIFICATIONS AND MANUFACTURING ENHANCEMENTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10820260
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Filing Dt:
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04/07/2004
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
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Patent #:
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Issue Dt:
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07/22/2008
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Application #:
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11074882
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Filing Dt:
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03/07/2005
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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INTERMEDIATE LAYOUT FOR RESOLUTION ENHANCEMENT IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11089723
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Filing Dt:
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03/24/2005
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Publication #:
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Pub Dt:
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10/19/2006
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Title:
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FLEXIBLE SHAPE IDENTIFICATION FOR OPTICAL PROXIMITY CORRECTION IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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11145025
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Filing Dt:
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06/03/2005
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Title:
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GATE-LENGTH BIASING FOR DIGITAL CIRCUIT OPTIMIZATION
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11169188
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Filing Dt:
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06/27/2005
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Publication #:
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Pub Dt:
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12/28/2006
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Title:
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METHODS FOR CREATING PRIMITIVE CONSTRUCTED STANDARD CELLS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11199900
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Filing Dt:
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08/08/2005
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Publication #:
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Pub Dt:
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02/08/2007
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Title:
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Method and system for reshaping metal wires in VLSI design
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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11254643
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Filing Dt:
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10/19/2005
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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METHOD AND SYSTEM FOR FINDING AN EQUIVALENT CIRCUIT REPRESENTATION FOR ONE OR MORE ELEMENTS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/12/2010
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Application #:
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11267686
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Filing Dt:
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11/04/2005
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Publication #:
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Pub Dt:
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05/25/2006
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Title:
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METHOD AND SYSTEM FOR TOPOGRAPHY-AWARE RETICLE ENHANCEMENT
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Patent #:
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Issue Dt:
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12/29/2009
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Application #:
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11331605
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Filing Dt:
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01/14/2006
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Publication #:
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Pub Dt:
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07/19/2007
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Title:
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METHOD AND SYSTEM FOR PLACING LAYOUT OBJECTS IN A STANDARD-CELL LAYOUT
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Patent #:
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Issue Dt:
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12/01/2009
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Application #:
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11386268
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Filing Dt:
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03/21/2006
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Title:
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SYSTEM AND METHOD FOR VARYING THE STARTING CONDITIONS FOR A RESOLUTION ENHANCEMENT PROGRAM TO IMPROVE THE PROBABILITY THAT DESIGN GOALS WILL BE MET
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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11391771
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Filing Dt:
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03/28/2006
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Title:
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METHOD AND SYSTEM FOR RESHAPING A TRANSISTOR GATE IN AN INTEGRATED CIRCUIT TO ACHIEVE A TARGET OBJECTIVE
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11486511
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Filing Dt:
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07/14/2006
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Title:
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ARRANGEMENT OF FILL UNIT ELEMENTS IN AN INTEGRATED CIRCUIT INTERCONNECT LAYER
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Patent #:
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Issue Dt:
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03/09/2010
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Application #:
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11486936
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Filing Dt:
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07/13/2006
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Title:
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LAYOUT DESCRIPTION HAVING ENHANCED FILL ANNOTATION
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Patent #:
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Issue Dt:
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09/20/2011
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Application #:
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11499070
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Filing Dt:
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08/04/2006
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Title:
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METHOD AND SYSTEM FOR WAFER TOPOGRAPHY-AWARE INTEGRATED CIRCUIT DESIGN ANALYSIS AND OPTIMIZATION
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11590581
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Filing Dt:
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10/31/2006
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Title:
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METHOD OF DESIGNING A DIGITAL CIRCUIT BY CORRELATING DIFFERENT STATIC TIMING ANALYZERS
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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11602043
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Filing Dt:
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11/20/2006
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Title:
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METHOD AND SYSTEM FOR INTEGRATED CIRCUIT OPTIMIZATION BY USING AN OPTIMIZED STANDARD-CELL LIBRARY
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Patent #:
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Issue Dt:
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09/15/2009
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Application #:
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11680552
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Filing Dt:
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02/28/2007
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Title:
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METHODS FOR RISK-INFORMED CHIP LAYOUT GENERATION
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11683402
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Filing Dt:
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03/07/2007
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Publication #:
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Pub Dt:
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09/13/2007
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Title:
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DYNAMIC ARRAY ARCHITECTURE
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Patent #:
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Issue Dt:
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09/08/2009
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Application #:
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11836088
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Filing Dt:
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08/08/2007
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Title:
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MEMORY TIMING APPARATUS AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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08/18/2009
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Application #:
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11836099
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Filing Dt:
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08/08/2007
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Title:
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SPECULATIVE SENSE ENABLE TUNING APPARATUS AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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11956305
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Filing Dt:
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12/13/2007
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Publication #:
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Pub Dt:
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06/18/2009
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Title:
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SUPER-SELF-ALIGNED CONTACTS AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11969854
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Filing Dt:
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01/04/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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12013342
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Filing Dt:
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01/11/2008
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Publication #:
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Pub Dt:
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02/05/2009
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH DYNAMIC ARRAY SECTION
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Patent #:
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Issue Dt:
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03/15/2011
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Application #:
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12013356
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Filing Dt:
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01/11/2008
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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METHODS FOR DESIGNING SEMICONDUCTOR DEVICE WITH DYNAMIC ARRAY SECTION
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12013366
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Filing Dt:
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01/11/2008
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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METHODS FOR DEFINING DYNAMIC ARRAY SECTION WITH MANUFACTURING ASSURANCE HALO AND APPARATUS IMPLEMENTING THE SAME
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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12021722
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Filing Dt:
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01/29/2008
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Publication #:
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Pub Dt:
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05/22/2008
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Title:
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METHODS FOR CREATING PRIMITIVE CONSTRUCTED STANDARD CELLS
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12033807
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Filing Dt:
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02/19/2008
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Publication #:
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Pub Dt:
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12/02/2010
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Title:
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INTEGRATED CIRCUIT CELL LIBRARY WITH CELL-LEVEL PROCESS COMPENSATION TECHNIQUE (PCT) APPLICATION AND ASSOCIATED METHODS
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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12041584
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Filing Dt:
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03/03/2008
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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INTEGRATED CIRCUIT CELL LIBRARY FOR MULTIPLE PATTERNING
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12075654
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Filing Dt:
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03/12/2008
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Title:
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SYSTEM AND METHOD FOR PERFORMING TRANSISTOR-LEVEL STATIC PERFORMANCE ANALYSIS USING CELL-LEVEL STATIC ANALYSIS TOOLS
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12099663
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Filing Dt:
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04/08/2008
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Publication #:
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Pub Dt:
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09/04/2008
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Title:
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INTERMEDIATE LAYOUT FOR RESOLUTION ENHANCEMENT IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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12212353
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Filing Dt:
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09/17/2008
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Title:
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GATE-LENGTH BIASING FOR DIGITAL CIRCUIT OPTIMIZATION
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Patent #:
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Issue Dt:
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11/30/2010
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Application #:
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12212562
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Filing Dt:
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09/17/2008
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Publication #:
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Pub Dt:
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01/15/2009
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Title:
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DYNAMIC ARRAY ARCHITECTURE
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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12271907
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Filing Dt:
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11/16/2008
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Publication #:
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Pub Dt:
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05/21/2009
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Title:
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DIFFUSION VARIABILITY CONTROL AND TRANSISTOR DEVICE SIZING USING THRESHOLD VOLTAGE IMPLANT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12288793
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Filing Dt:
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10/23/2008
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Publication #:
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Pub Dt:
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04/29/2010
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Title:
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Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12340406
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Filing Dt:
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12/19/2008
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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METHODS AND SYSTEMS FOR PROCESS COMPENSATION TECHNIQUE ACCELERATION
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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12363705
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Filing Dt:
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01/30/2009
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Publication #:
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Pub Dt:
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09/10/2009
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Title:
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Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12399948
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Filing Dt:
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03/07/2009
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Publication #:
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Pub Dt:
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09/10/2009
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Title:
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METHODS FOR DEFINING CONTACT GRID IN DYNAMIC ARRAY ARCHITECTURE
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12402465
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Filing Dt:
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03/11/2009
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Publication #:
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Pub Dt:
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09/10/2009
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Title:
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CROSS-COUPLED TRANSISTOR LAYOUTS IN RESTRICTED GATE LEVEL LAYOUT ARCHITECTURE
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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12411249
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Filing Dt:
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03/25/2009
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Publication #:
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Pub Dt:
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09/10/2009
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Title:
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METHODS FOR MULTI-WIRE ROUTING AND APPARATUS IMPLEMENTING SAME
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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12435672
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Filing Dt:
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05/05/2009
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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Circuitry and Layouts for XOR and XNOR Logic
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Patent #:
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Issue Dt:
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01/05/2016
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Application #:
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12466335
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Filing Dt:
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05/14/2009
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Publication #:
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Pub Dt:
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11/19/2009
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Title:
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Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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12466341
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Filing Dt:
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05/14/2009
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Publication #:
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Pub Dt:
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09/10/2009
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Title:
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OVERSIZED CONTACTS AND VIAS IN SEMICONDUCTOR CHIP DEFINED BY LINEARLY CONSTRAINED TOPOLOGY
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07/17/2012
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12479674
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06/05/2009
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Pub Dt:
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12/03/2009
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Title:
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METHODS FOR DEFINING AND UTILIZING SUB-RESOLUTION FEATURES IN LINEAR TOPOLOGY
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12481445
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Filing Dt:
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06/09/2009
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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Optimizing Layout of Irregular Structures in Regular Layout Context
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Patent #:
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Issue Dt:
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08/14/2012
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Application #:
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12484130
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Filing Dt:
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06/12/2009
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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METHODS FOR DEFINING AND USING CO-OPTIMIZED NANOPATTERNS FOR INTEGRATED CIRCUIT DESIGN AND APPARATUS IMPLEMENTING SAME
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Patent #:
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Issue Dt:
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07/03/2012
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Application #:
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12497052
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07/02/2009
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Publication #:
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Pub Dt:
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10/29/2009
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Title:
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METHODS FOR CELL PHASING AND PLACEMENT IN DYNAMIC ARRAY ARCHITECTURE AND IMPLEMENTATION OF THE SAME
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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12512932
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Filing Dt:
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07/30/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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METHODS FOR CONTROLLING MICROLOADING VARIATION IN SEMICONDUCTOR WAFER LAYOUT AND FABRICATION
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Issue Dt:
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04/26/2011
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12561207
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/07/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS INCLUDING LINEAR CONDUCTIVE SEGMENTS HAVING NON-GATE EXTENSION PORTIONS
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Issue Dt:
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03/15/2011
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Application #:
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12561216
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS HAVING TRANSISTORS FORMED FROM SIX LINEAR CONDUCTIVE SEGMENTS WITH INTERVENING DIFFUSION CONTACT RESTRICTIONS
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12561220
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUT HAVING THREE OR MORE LINEAR-SHAPED GATE ELECTRODE LEVEL CONDUCTIVE SEGMENTS OF BOTH EQUAL LENGTH AND EQUAL PITCH
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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12561224
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE HAVING 1965 NM GATE ELECTRODE LEVEL REGION INCLUDING AT LEAST FOUR ACTIVE LINEAR CONDUCTIVE SEGMENTS AND AT LEAST ONE NON-GATE LINEAR CONDUCTIVE SEGMENT
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12561229
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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INTEGRATED CIRCUIT AND ASSOCIATED LAYOUT WITH GATE ELECTRODE LEVEL PORTION INCLUDING AT LEAST TWO COMPLIMENTARY TRANSISTOR FORMING LINEAR CONDUCTIVE SEGMENTS AND AT LEAST ONE NON-GATE LINEAR CONDUCTIVE SEGMENT
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Patent #:
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Issue Dt:
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08/02/2011
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Application #:
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12561234
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE HAVING LINEAR-SHAPED GATE ELECTRODES OF DIFFERENT TRANSISTOR TYPES WITH UNIFORMITY EXTENDING PORTIONS OF DIFFERENT LENGTHS
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12561238
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS INCLUDING DIFFUSION CONTACT PLACEMENT RESTRICTION BASED ON RELATION TO LINEAR CONDUCTIVE SEGMENTS
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Patent #:
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Issue Dt:
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08/02/2011
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Application #:
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12561243
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE HAVING AT LEAST FOUR SIDE-BY-SIDE GATE ELECTRODES OF EQUAL LENGTH AND EQUAL PITCH WITH AT LEAST TWO TRANSISTOR CONNECTIONS TO POWER OR GROUND
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12561246
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE HAVING TWO PAIRS OF TRANSISTORS OF DIFFERENT TYPES FORMED FROM SHARED LINEAR-SHAPED CONDUCTIVE FEATURES WITH INTERVENING TRANSISTORS OF COMMON TYPE ON EQUAL PITCH
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Patent #:
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Issue Dt:
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09/20/2011
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Application #:
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12561247
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Filing Dt:
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09/16/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS HAVING TRANSISTORS FORMED FROM SIX LINEAR CONDUCTIVE SEGMENTS WITH GATE ELECTRODE-TO-GATE ELECTRODE CONNECTION THROUGH SINGLE INTERCONNECT LEVEL AND COMMON NODE CONNECTION THROUGH DIFFERENT INTERCONNECT LEVEL
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12563031
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS HAVING TRANSISTORS FORMED FROM LINEAR CONDUCTIVE SEGMENT WITH NON-ACTIVE NEIGHBORING LINEAR CONDUCTIVE SEGMENT
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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12563042
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS INCLUDING GATE ELECTRODE LEVEL REGION HAVING ARRANGEMENT OF SIX LINEAR CONDUCTIVE SEGMENTS WITH SIDE-TO-SIDE SPACING LESS THAN 360 NANOMETERS
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12563051
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE HAVING AT LEAST THREE LINEAR-SHAPED ELECTRODE LEVEL CONDUCTIVE FEATURES OF EQUAL LENGTH POSITIONED SIDE-BY-SIDE AT EQUAL PITCH
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Patent #:
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Issue Dt:
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10/04/2011
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Application #:
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12563056
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE AND ASSOCIATED LAYOUT INCLUDING SEPARATED DIFFUSION REGIONS OF DIFFERENT TYPE EACH HAVING FOUR GATE ELECTRODES WITH EACH OF TWO COMPLEMENTARY GATE ELECTRODE PAIRS FORMED FROM RESPECTIVE LINEAR CONDUCTIVE SEGMENT
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Patent #:
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Issue Dt:
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12/06/2011
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Application #:
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12563061
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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INTEGRATD CIRCUIT DEVICE AND ASSOCIATED LAYOUT INCLUDING TWO PAIRS OF CO-ALIGNED COMPLEMENTARY GATE ELECTRODES WITH OFFSET GATE CONTACT STRUCTURES
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12563063
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE AND ASSOCIATED LAYOUT INCLUDING LINEAR GATE ELECTRODES OF DIFFERENT TRANSISTOR TYPES NEXT TO LINEAR-SHAPED NON-GATE CONDUCTIVE SEGMENT
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12563066
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS HAVING LINEAR SHAPED GATE ELECTRODES DEFINED ALONG AT LEAST FIVE ADJACENT GATE ELECTRODE TRACKS OF EQUAL PITCH WITH GATE ELECTRODE CONNECTION THROUGH SINGLE INTERCONNECT LEVEL
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Patent #:
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|
Issue Dt:
|
01/03/2012
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Application #:
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12563074
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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METHOD FOR FABRICATING INTEGRATED CIRCUIT WITH GATE ELECTRODE LEVEL PORTION INCLUDING AT LEAST TWO COMPLEMENTARY TRANSISTOR FORMING LINEAR CONDUCTIVE SEGMENTS AND AT LEAST ONE NON-GATE LINEAR CONDUCTIVE SEGMENT
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Patent #:
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Issue Dt:
|
09/04/2012
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Application #:
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12563076
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH LINEARLY RESTRICTED GATE LEVEL REGION INCLUDING TWO TRANSISTORS OF FIRST TYPE AND TWO TRANSISTORS OF SECOND TYPE WITH OFFSET GATE CONTACTS
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Patent #:
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|
Issue Dt:
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01/03/2012
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Application #:
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12563077
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE AND ASSOCIATED LAYOUT INCLUDING GATE ELECTRODE LEVEL REGION OF 965 NM RADIUS WITH LINEAR-SHAPED CONDUCTIVE SEGMENTS ON FIXED PITCH
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12567528
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT WITH GATE ELECTRODE LEVEL REGION INCLUDING AT LEAST FOUR LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTORS AND INCLUDING EXTENDING PORTIONS OF AT LEAST TWO DIFFERENT SIZES
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Patent #:
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|
Issue Dt:
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03/06/2012
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Application #:
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12567542
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
|
INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTORS WITH AT LEAST TWO LINEAR-SHAPED CONDUCTIVE STRUCTURES OF DIFFERENT LENGTH
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Patent #:
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|
Issue Dt:
|
03/06/2012
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Application #:
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12567555
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES AND INCLUDING FOUR CONDUCTIVE CONTACTING STRUCTURES HAVING AT LEAST TWO DIFFERENT CONNECTION DISTANCES
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Patent #:
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|
Issue Dt:
|
03/06/2012
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Application #:
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12567565
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING A LINEAR-SHAPED CONDUCTIVE STRUCTURE FORMING ONE GATE ELECTRODE AND HAVING LENGTH GREATER THAN OR EQUAL TO ONE-HALF THE LENGTH OF LINEAR-SHAPED CONDUCTIVE STRUCTURE FORMING TWO GATE ELECTRODES
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Patent #:
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|
Issue Dt:
|
02/07/2012
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Application #:
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12567574
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE WITH LINEARLY DEFINED GATE ELECTRODE LEVEL REGION AND SHARED DIFFUSION REGION OF FIRST TYPE CONNECTED TO SHARED DIFFUSION REGION OF SECOND TYPE THROUGH AT LEAST TWO INTERCONNECT LEVELS
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|
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Patent #:
|
|
Issue Dt:
|
01/03/2012
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Application #:
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12567586
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE WITH GATE ELECTRODE LEVEL REGION INCLUDING TWO SIDE-BY-SIDE ONES OF AT LEAST THREE LINEAR-SHAPED CONDUCTIVE STRUCTURES ELECTRICALLY CONNECTED TO EACH OTHER THROUGH NON-GATE LEVEL
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Patent #:
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|
Issue Dt:
|
01/03/2012
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Application #:
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12567597
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
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Title:
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METHOD FOR FABRICATING INTEGRATED CIRCUIT HAVING THREE OR MORE LINEAR-SHAPED GATE ELECTRODE LEVEL CONDUCTIVE SEGMENTS OF BOTH EQUAL LENGTH AND EQUAL PITCH
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Patent #:
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|
Issue Dt:
|
01/24/2012
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Application #:
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12567602
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
|
02/11/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE WITH GATE LEVEL REGION INCLUDING NON-GATE LINEAR CONDUCTIVE SEGMENT POSITIONED WITHIN 965 NANOMETERS OF FOUR TRANSISTORS OF FIRST TYPE AND FOUR TRANSISTORS OF SECOND TYPE
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Patent #:
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|
Issue Dt:
|
01/03/2012
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Application #:
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12567609
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT DEVICE WITH GATE LEVEL REGION INCLUDING AT LEAST THREE LINEAR-SHAPED CONDUCTIVE SEGMENTS HAVING OFFSET LINE ENDS AND FORMING THREE TRANSISTORS OF FIRST TYPE AND ONE TRANSISTOR OF SECOND TYPE
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Patent #:
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|
Issue Dt:
|
03/13/2012
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Application #:
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12567616
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING LINEAR-SHAPED CONDUCTIVE STRUCTURES THAT HAVE GATE PORTIONS AND EXTENDING PORTIONS OF DIFFERENT SIZE
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|
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Patent #:
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|
Issue Dt:
|
06/26/2012
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Application #:
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12567623
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
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01/21/2010
| | | | |
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Title:
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METHODS OF FABRICATING AND CREATING LAYOUT FOR INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTORS WITH AT LEAST TWO LINEAR-SHAPED CONDUCTIVE STRUCTURES OF DIFFERENT LENGTH
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|
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Patent #:
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|
Issue Dt:
|
05/24/2011
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Application #:
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12567630
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Filing Dt:
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09/25/2009
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Publication #:
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Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS HAVING LINEAR SHAPED GATE ELECTRODES DEFINED ALONG AT LEAST FIVE ADJACENT GATE ELECTRODE TRACKS OF EQUAL PITCH
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|
|
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Patent #:
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|
Issue Dt:
|
03/06/2012
|
Application #:
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12567634
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Filing Dt:
|
09/25/2009
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Publication #:
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|
Pub Dt:
|
01/21/2010
| | | | |
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Title:
|
METHOD OF FABRICATING INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES AT EQUAL PITCH INCLUDING AT LEAST TWO LINEAR-SHAPED CONDUCTIVE STRUCTURES HAVING NON-GATE PORTIONS OF DIFFERENT LENGTH
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|
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Patent #:
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|
Issue Dt:
|
03/13/2012
|
Application #:
|
12567641
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Filing Dt:
|
09/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING GATE ELECTRODE LEVEL REGION INCLUDING AT LEAST FOUR LINEAR-SHAPED CONDUCTIVE STRUCTURES WITH SOME OUTER-CONTACTED LINEAR-SHAPED CONDUCTIVE STRUCTURES HAVING LARGER OUTER EXTENDING PORTION THAN INNER EXTENDING PORTION
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|
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Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12567648
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Filing Dt:
|
09/25/2009
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|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING GATE ELECTRODE LEVEL REGION INCLUDING AT LEAST SEVEN LINEAR-SHAPED CONDUCTIVE STRUCTURES OF EQUAL LENGTH POSITIONED AT EQUAL PITCH WITH AT LEAST TWO LINEAR-SHAPED CONDUCTIVE STRUCTURES EACH FORMING ONE TRANSISTOR AND HAVING EXTENDING PORTION SIZED GREATER THAN GATE PORTION
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|
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Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12567654
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Filing Dt:
|
09/25/2009
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|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
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Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12571343
|
Filing Dt:
|
09/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH GATE ELECTRODE LEVEL INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTERS WITH AT LEAST ONE PAIR OF LINEAR-SHAPED CONDUCTIVE STRUCTURES HAVING OFFSET ENDS
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|
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Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
12571351
|
Filing Dt:
|
09/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING GATE ELECTRODE LEVEL REGION INCLUDING AT LEAST THREE LINEAR-SHAPED CONDUCTIVE STRUCTURES OF EQUAL LENGTH HAVING ALIGNED ENDS AND POSITIONED AT EQUAL PITCH AND FORMING MULTIPLE GATE ELECTRODES OF TRANSISTORS OF DIFFERENT TYPE
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|
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Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12571357
|
Filing Dt:
|
09/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING GATE ELECTRODE LEVEL REGION INCLUDING AT LEAST FOUR LINEAR-SHAPED CONDUCTIVE STRUCTURES OF EQUAL LENGTH HAVING ALIGNED ENDS AND POSITIONED AT EQUAL PITCH AND FORMING MULTIPLE GATE ELECTRODES OF TRANSISTORS OF DIFFERENT TYPE
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|
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Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12571998
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH GATE LEVEL INCLUDING FOUR TRANSISTORS OF FIRST TYPE AND FOUR TRANSISTORS OF SECOND TYPE SEPARATED BY NON-DIFFUSION REGION WITH RESTRICTED GATE CONTACT PLACEMENT OVER SEPARATING NON-DIFFUSION REGION
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|
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Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12572011
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Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH LINEARLY RESTRICTED GATE LEVEL REGION INCLUDING FOUR SERIALLY CONNECTED TRANSISTORS OF FIRST TYPE AND FOUR SERIALLY CONNECTED TRANSISTORS OF SECOND TYPE SEPARATED BY NON-DIFFUSION REGION
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|
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Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12572022
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH GATE LEVEL INCLUDING FOUR TRANSISTORS OF FIRST TYPE AND FOUR TRANSISTORS OF SECOND TYPE SEPARATED BY NON-DIFFUSION REGION AND HAVING AT LEAST TWO GATE CONTACTS POSITIONED OUTSIDE SEPARATING NON-DIFFUSION REGION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12572046
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING AT LEAST SIX TRANSISTOR FORMING LINEAR SHAPES INCLUDING AT LEAST TWO DIFFERENT GATE CONTACT CONNECTION DISTANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12572055
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12572061
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING AT LEAST THREE LINEAR-SHAPED CONDUCTIVE STRUCTURES OF DIFFERENT LENGTH EACH FORMING GATE OF DIFFERENT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12572068
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING AT LEAST SIX TRANSISTOR FORMING LINEAR SHAPES INCLUDING AT LEAST TWO TRANSISTOR FORMING LINEAR SHAPES HAVING DIFFERENT EXTENSION DISTANCES BEYOND GATE CONTACT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
12572077
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND ASSOCIATED LAYOUTS HAVING TRANSISTORS FORMED FROM SIX LINEAR CONDUCTIVE SEGMENTS WITH GATE ELECTRODE CONNECTION THROUGH SINGLE INTERCONNECT LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
12572091
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
METHOD FOR FABRICATING INTEGRATED CIRCUIT HAVING AT LEAST THREE LINEAR-SHAPED GATE ELECTRODE LEVEL CONDUCTIVE FEATURES OF EQUAL LENGTH POSITIONED SIDE-BY-SIDE AT EQUAL PITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
12572194
|
Filing Dt:
|
10/01/2009
|
|
Publication #:
|
|
Pub Dt:
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02/11/2010
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Title:
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METHOD FOR FABRICATING INTEGRATED CIRCUIT INCLUDING SEPARATED DIFFUSION REGIONS OF DIFFERENT TYPE EACH HAVING FOUR GATE ELECTRODES WITH EACH OF TWO COMPLEMENTARY GATE ELECTRODE PAIRS FORMED FROM RESPECTIVE LINEAR CONDCUTIVE SEGMENT
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12572201
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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INTEGRATED CIRCUIT WITH GATE ELECTRODE LEVEL REGION INCLUDING MULTIPLE LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTORS AND INCLUDING UNIFORMITY EXTENDING PORTIONS OF DIFFERENT SIZE
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12572212
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR FORMING LINEAR SHAPES INCLUDING GATE PORTIONS AND EXTENDING PORTIONS OF DIFFERENT SIZE
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12572218
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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INTEGRATED CIRCUIT WITH GATE ELECTRODE LEVEL INCLUDING AT LEAST FOUR LINEAR-SHAPED CONDUCTIVE STRUCTURES OF EQUAL LENGTH AND EQUAL PITCH WITH LINEAR-SHAPED CONDUCTIVE STRUCTURE FORMING ONE TRANSISTOR
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