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Reel/Frame:064746/0409   Pages: 6
Recorded: 08/29/2023
Attorney Dkt #:REFILE-11
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED ON REEL 058297 FRAME 0646. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Total properties: 20
1
Patent #:
Issue Dt:
04/26/2005
Application #:
10160646
Filing Dt:
05/31/2002
Publication #:
Pub Dt:
12/05/2002
Title:
METHODS OF FORMING IINTEGRATED CIRCUIT DEVICES HAVING A METAL-INSULATOR-METAL (MIM) CAPACITOR
2
Patent #:
Issue Dt:
05/04/2004
Application #:
10222573
Filing Dt:
08/15/2002
Publication #:
Pub Dt:
03/06/2003
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING SHARED ROW SELECTION CIRCUIT
3
Patent #:
Issue Dt:
02/27/2007
Application #:
10819385
Filing Dt:
04/05/2004
Publication #:
Pub Dt:
02/01/2007
Title:
FLASH MEMORY DEVICE CAPABLE OF PREVENTING PROGRAM DISTURBANCE ACCORDING TO PARTIAL PROGRAMMING
4
Patent #:
Issue Dt:
08/08/2006
Application #:
10848913
Filing Dt:
05/18/2004
Publication #:
Pub Dt:
03/03/2005
Title:
DATA DRIVING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
5
Patent #:
Issue Dt:
08/01/2006
Application #:
10860947
Filing Dt:
06/04/2004
Publication #:
Pub Dt:
12/09/2004
Title:
DELAY STAGE INSENSITIVE TO OPERATING VOLTAGE AND DELAY CIRCUIT INCLUDING THE SAME
6
Patent #:
Issue Dt:
07/11/2006
Application #:
10889194
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
01/13/2005
Title:
REDUNDANCY CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE HAVING A MULTIBLOCK STRUCTURE
7
Patent #:
Issue Dt:
11/28/2006
Application #:
10919370
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
06/16/2005
Title:
INPUT SIGNAL RECEIVING DEVICE OF SEMICONDUCTOR MEMORY UNIT
8
Patent #:
Issue Dt:
03/27/2007
Application #:
10937519
Filing Dt:
09/09/2004
Publication #:
Pub Dt:
06/09/2005
Title:
PACKET ADDRESSING PROGRAMMABLE DUAL PORT MEMORY DEVICES AND RELATED METHODS
9
Patent #:
Issue Dt:
02/13/2007
Application #:
10940808
Filing Dt:
08/24/2004
Publication #:
Pub Dt:
06/16/2005
Title:
MULTI-LEVEL HIGH VOLTAGE GENERATOR
10
Patent #:
Issue Dt:
09/26/2006
Application #:
10976626
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
07/07/2005
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SCALABLE TWO TRANSISTOR MEMORY CELLS
11
Patent #:
Issue Dt:
07/25/2006
Application #:
10991042
Filing Dt:
11/16/2004
Publication #:
Pub Dt:
05/26/2005
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER WITH INCREASED SPEED
12
Patent #:
Issue Dt:
01/09/2007
Application #:
10992963
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
08/04/2005
Title:
SEMICONDUCTOR MEMORY DEVICE WITH CYLINDRICAL STORAGE ELECTRODE AND METHOD OF MANUFACTURING THE SAME
13
Patent #:
Issue Dt:
02/19/2008
Application #:
11020277
Filing Dt:
12/27/2004
Publication #:
Pub Dt:
06/30/2005
Title:
METHOD OF FORMING AN INTERCONNECTION LINE IN A SEMICONDUCTOR DEVICE
14
Patent #:
Issue Dt:
05/08/2007
Application #:
11025765
Filing Dt:
12/28/2004
Publication #:
Pub Dt:
03/23/2006
Title:
HIGH VOLTAGE GENERATOR CIRCUIT WITH RIPPLE STABILIZATION FUNCTION
15
Patent #:
Issue Dt:
08/29/2006
Application #:
11118229
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
02/09/2006
Title:
FIXED OFFSET DIGITAL-TO-ANALOG CONVERSION DEVICE AND METHOD
16
Patent #:
Issue Dt:
04/03/2007
Application #:
11147629
Filing Dt:
06/08/2005
Publication #:
Pub Dt:
12/29/2005
Title:
DUTY CYCLE CORRECTION CIRCUIT FOR USE IN A SEMICONDUCTOR DEVICE
17
Patent #:
Issue Dt:
05/29/2007
Application #:
11166620
Filing Dt:
06/24/2005
Publication #:
Pub Dt:
05/18/2006
Title:
CIRCUIT AND METHOD FOR GENERATING WORDLINE VOLTAGE IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
18
Patent #:
Issue Dt:
03/02/2010
Application #:
11512155
Filing Dt:
08/30/2006
Publication #:
Pub Dt:
12/28/2006
Title:
DUTY CYCLE CORRECTION CIRCUIT OF DELAY LOCKED LOOP AND DELAY LOCKED LOOP HAVING THE DUTY CYCLE CORRECTION CIRCUIT
19
Patent #:
Issue Dt:
08/24/2010
Application #:
12270286
Filing Dt:
11/13/2008
Publication #:
Pub Dt:
03/19/2009
Title:
SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF
20
Patent #:
Issue Dt:
11/18/2014
Application #:
13405703
Filing Dt:
02/27/2012
Title:
DUTY CYCLE CORRECTION CIRCUIT OF DELAY LOCKED LOOP AND DELAY LOCKED LOOP HAVING THE DUTY CYCLE CORRECTION CIRCUIT
Assignor
1
Exec Dt:
04/01/2021
Assignee
1
515 LEGGET DRIVE
SUITE 100
OTTAWA, CANADA K2K 3G4
Correspondence name and address
CONVERSANT IP MANAGEMENT CORP.
5830 GRANITE PARKWAY #100-247
PLANO, TX 75024

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